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franco.polo
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ADC section done.-
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‎Cpp/65_adc/App/main.cpp‎

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#include "uart.h"
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#include "stdio.h"
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#include "adc.h"
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std::uint32_t sensorVal;
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int main(void){
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/*Init USART6*/
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uart6_init();
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/*ADC1 Init*/
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adc1_init();
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/*Superloop*/
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while(true){
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/*Read ADC*/
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sensorVal = adc1_get();
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}
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}

‎Cpp/65_adc/DebugConfig/STM32f407_STM32F407IGHx.dbgconf‎

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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
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// refer to STM32F40x STM32F41x datasheets
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// refer to STM32F42x STM32F43x datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// <o.1> DBG_STOP <i> Debug Stop Mode
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// <o.0> DBG_SLEEP <i> Debug Sleep Mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
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// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
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// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
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// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
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// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <<< end of configuration section >>>

‎Cpp/65_adc/DebugConfig/Target_1_STM32F407IGHx.dbgconf‎

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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
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// refer to STM32F40x STM32F41x datasheets
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// refer to STM32F42x STM32F43x datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// <o.1> DBG_STOP <i> Debug Stop Mode
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// <o.0> DBG_SLEEP <i> Debug Sleep Mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
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// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
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// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
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// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
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// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <<< end of configuration section >>>

‎Cpp/65_adc/Drivers/adc.cpp‎

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#include "adc.h"
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#define ADC1((mcal::reg::ADC_TypeDef*)mcal::reg::adc1_base)
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void adc1_init(void){
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/*Enable clock access to PA1*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::ahb1enr,
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(1U<<0)
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>::reg_or();
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/*Configure PA1 as analog*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::gpioa_moder,
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(1U<<2)
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>::reg_or();
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::gpioa_moder,
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(1U<<3)
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>::reg_or();
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//mcal::reg::reg_access<
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//std::uint32_t,
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//std::uint32_t,
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//mcal::reg::ahb1enr,
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//(0x0C)
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// >::reg_or();
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/*Enable clock access to adc1*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::apb2enr,
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(1U<<8)
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>::reg_or();
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/*SW trigger*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::adc1_cr2,
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(0x00)
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>::reg_set();
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/*Conversion sequence starts at channel1*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::adc1_sqr3,
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(1U<<0)
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>::reg_set();
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/*Conversion sequence length*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::adc1_sqr1,
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(0x00)
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>::reg_set();
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/*Enable ADC*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::adc1_cr2,
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(1U<<0)
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>::reg_or();
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}
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/*adc1_get*/
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std::uint32_t adc1_get(void){
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/*Start conversion*/
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mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::adc1_cr2,
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(1U<<30)
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>::reg_or();
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/*Wait for conversion*/
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while(!(ADC1->SR) & (0x02)){}
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/*Read value from data register*/
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return mcal::reg::reg_access<
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std::uint32_t,
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std::uint32_t,
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mcal::reg::adc1_dr,
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(1U<<30)
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>::reg_get();
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}

‎Cpp/65_adc/Drivers/adc.h‎

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#ifndef __ADC_H
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#define __ADC_H
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#include "mcal_reg.h"
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void adc1_init(void);
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std::uint32_t adc1_get(void);
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#endif // __ADC_H

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