How can this MIPS processor execute one instruction in one cycle?

Question

I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris.

At the end of the section the autor shows this MIPS processor and says that "Each instruction in the single-cycle processor takes one clock cycle".

The autor also says that "Result must setup at the register file before the next rising clock edge, so that it can be properly written". If I'm correct, he is saying that the processor has the whole cycle time to execute that instruction, but Result should be present at the rising edge of the clock of that same cycle because the PC, Register File and Data Memory are changed only during the clock edge. Thus, the processor has only the rising time, not the cycle time, to execute the instruction.

I don't understand how he can say that an instruction can be executed in one cycle time if the elements are chained like that and even the Register File has to wait for its own result to be processed and arrive at WD3 in the same cycle.

Pseudonym · Accepted Answer · 2022-04-13 01:31:12Z

The register file in this design is multi-ported, and the read ports work like combinational circuits. The only thing between the read input and the output port is propagation delay. The clock signal is only needed to write a value.

The same is true for data memory, which is assumed to be a combinational circuit for the purpose of issuing a read.

If the value of a register is modified, and then the same register is read on the next instruction, then there may be a propagation delay before the newly-loaded value is valid at the read port, but that's a limitation on the clock speed, not on the correctness of the data path. As long as the input to a latch is correct at the time the latch is loaded, the CPU will work correctly.

I don't understand. The signals follow the data path (the dashed blue line). What I think is that they must complete their path and arrive at WD3 before the rising edge finishes, because the clocked elements only accept signal on the rising edge. Is this correct? — EmTor
– EmTor, Commented Apr 13, 2022 at 3:38
The clocked elements only accept their signal on the rising edge, that is correct. The read ports on the data memory and the register file are NOT clocked elements. Only the write ports are. — Pseudonym
– Pseudonym ♦, Commented Apr 13, 2022 at 7:46

Giovanni · Accepted Answer · 2024-10-18 08:55:46Z

You have conflated different concepts together, and probably lack understanding of how processor architectures are implemented as VLSI systems (or digital integrated circuits).

The registers for implementing synchronous sequential logic circuits, or simply sequential circuits, are typically realized/implemented with flip-flops, rather than latches.

It is (much/far) more common to use flip-flops, rather than latches, since they only take in values for each clock cycle at the rising edge of the clock or the falling edge of the clock exclusively.

Else, the use of latches mean that the values of the output port would be updated throughout the clock cycle. This can make it harder to implement finite state machines as sequential circuits that track which state the sequential circuits are in.

The use of the rising edge of the clock, rather than the falling edge of the clock, is due to designer's choice. It does not really matter which edge do you choose.

Hence, with each rising clock edge, the flip-flops implementing registers in synchronous sequential circuits will read input data to bring the synchronous sequential circuits into the next state of the finite state machine, or remain in the same state.

By selecting a clock cycle with a period significantly longer than the propagation delay for logic signals to propagate from the 1st stage (i.e., instruction fetch) of the processor architecture (or microarchitecture) to the last stage (i.e., write back stage), for the processing of each instruction in the instruction set architecture (ISA), the single-cycle processor can execute each instruction in one clock cycle. This is true for all ISAs, from MIPS to ARM to RISC-V to x86 to x86-64.

I voted on the other answer, which is fairly correct, except that the explanation about latches is incorrect. Hence, I mentioned it to help people understand how registers can be implemented with flip-flops or latches, but IC designers usually use flip-flops. — Giovanni
– Giovanni, Commented Oct 19, 2024 at 6:38

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