Questions tagged [mips]

Question 1

In a mock exam for my CS course in computer architecture there is the question: "explain why the multicycle datapath is faster than the single cycle datapath." The TA wrote the answer: "...

Question 2

In a pipelined MIPS CPU, writing to the pipeline registers, registers and PC occurs when the in the rising edge of the clock, and reading occurs in the falling edge, according to my understanding. ...

Question 3

I am stumbling over the Exercise 2.3 of Chapter 2, i.e.: For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, <...

Question 4

I was reading Computer Architecture Organization and Design by David A. Patterson and John L. Hennessy. Specifically, I was reading chapter 5, section 5.3, Basics of Caches. I read the following ...

Question 5

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Question 6

Consider the figure in Exercise 2. If the current machine code that executes is 0x214bfffd and the values of the registers in the processor are as shown below, what is then the value of the input WD3 ?...

Question 7

C++ code: int main() { short int arr[4][4]; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { arr[i][j] = i+j; } } return 0; } Is there ...

Question 8

probably a couple decades too late to ask this question, but does anyone know anything/have detailed documentation about the hardware/design underlying the ALU unit in the early MIPS R2000 CPU? ...

Question 9

I've recently learnt the execution of MIPS instruction set using single cycle processor. However I'm not getting one thing. Since one clock cycle is needed for the complete instruction we only have ...

Question 10

Use the five-stage pipeline with forwarding unit. add $t1, $t2, $t3 sw $t1, 0($t4) In the above code, is the data hazard of t1 fixed by forwarding the correct t1 ...

Question 11

I'm doing an exercise about the MIPS pipeline with the following characteristics: -Branches and Branch targets are calculated in the E-stage. -There is forward logic from the output to the input of ...

Question 12

This MIPS code is given: ...

Question 13

I'm reading section 7.3 (SINGLE CYCLE PROCESSOR) of Digital Design and Computer Architecture, Second Edition by David Money Harris. At the end of the section the autor shows this MIPS processor and ...

Question 14

Apparently, each stage of the MIPS processor pipeline takes one CPU cycle. According to this, a memory write can take more than one cycle: 1 cycle to read a register 4 cycles to reach to L1 cache 10 ...

Question 15

I am studying Computer Architecture with MIPS-32. The example system has 32 registers with each register having a width of 32 bit. If I would want 128 registers instead of 32 registers, would I have ...

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Questions tagged [mips]

velocity single cycle vs multicycle datapath

MIPS pipelined CPU Read and Write from Registers on First and Second Halves of Clock Cycle

Patterson & Hennessy, Computer Organization and Design, 5th edition, Question for Ex. 2.3

MIPS: How can the least 2 significant bits of a 32-bit address specify a byte?

Calculate the CPI of a program

How do you tell whether a binary number is positive or negative?

What is the hit rate of the cache when executing this code?

R2000 ALU Design

Execution of instruction in MIPS on various parts of the clock cycle

Data hazard in MIPS: SW after ADD

Why does it have that amount of stalls

Computer Architecture MIPS assembler with predictors

How can this MIPS processor execute one instruction in one cycle?

MIPS pipeline: MEM stage takes one cycle?

Do number of registers and width of register have to be the same?

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