Can the output of a D-type latch go metastable when:
- There is a minimum CLK/ENable pulse width violation
- The input and the output of the latch have the same value?
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- \$\begingroup\$ A very warm welcome to the site. I'm pretty certain it's a 'no' but I'm afraid I don't have the time to write the decent and substantiated answer this needs. \$\endgroup\$TonyM– TonyM2023-01-21 22:42:09 +00:00Commented Jan 21, 2023 at 22:42
- \$\begingroup\$ By latch, do you really mean latch or actually mean a flip-flop? (A latch lets its input flow to its output while its CLK/EN is at one level and holds its value while CLK/EN is at the opposite level. A flip-flop transfers input to output on a CLK edge,) \$\endgroup\$TonyM– TonyM2023-01-21 23:38:12 +00:00Commented Jan 21, 2023 at 23:38
- 1\$\begingroup\$ Any logic block is ideal, and the behaviour how it works under various conditions depends on the implementation. \$\endgroup\$Justme– Justme2023-01-21 23:43:18 +00:00Commented Jan 21, 2023 at 23:43
- \$\begingroup\$ I think OP means a latch, because the basic D-type flip flop does not have an enable. \$\endgroup\$SteveSh– SteveSh2023-01-22 01:03:10 +00:00Commented Jan 22, 2023 at 1:03
- \$\begingroup\$ @SteveSh, I think so too, but FPGA registers as FFs (eg a DFFE) have CLK and EN. OP: please edit your question to clarify what technology you are considering here and why. \$\endgroup\$TonyM– TonyM2023-01-22 10:47:40 +00:00Commented Jan 22, 2023 at 10:47
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