Questions tagged [metastability]
Questions about the behaviour of FlipFlops when the normal input setup or hold requrements are not respected, usually when launch and capture clocks are not synchronous.
47 questions
1 vote
1 answer
117 views
Can I do multi bit CDC using synchronizers without handshake or FIFO?
I know that asynchronous FIFO and handshake can do CDC, but the FIFO consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I ...
- 13
1 vote
2 answers
98 views
What is the metastable state of an SR latch?
Digital Design: Principles and Practice by John Wakerly (page 355) says that if the S and R inputs of an SR latch go from 1 to 0 simultaneously, the latch may "go into an unpredictable next state,...
- 111
7 votes
5 answers
1k views
FPGA metastability when going from a slow clock to faster clock?
I am new to FPGA, and I keep reading articles about how it is critical to double flop any sampled signal when going from a slow clock domain to a fast clock domain... https://nandland.com/lesson-14-...
- 10.4k
3 votes
1 answer
121 views
-2 votes
1 answer
145 views
Metastability between FPGA and C server via UART [closed]
I am planning to build a communication channel between my laptop (running a simple C server) and my FPGA using UART. Do I need to worry about metastability? I suppose to be more specific, I am ...
- 641
2 votes
1 answer
180 views
Worst case timing analysis for Setup and Hold time of a FF
Image Source: DDCA For Setup analysis, following waveform configuration is used: For Hold analysis, following waveform configuration is used: My question is: why the waveform below is not used for ...
- 631
0 votes
1 answer
123 views
How does a Lattice MachXO3LF FPGA handle undefined IO states?
In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this? How does the FPGA handle if the undefined state was reached ...
- 37
3 votes
1 answer
368 views
Metastability concern in bang-bang phase detector
Background The following is take from page 413 from Razavi's CMOS PLL book. This section (13.4.1) discusses bang-bang phase detector. As highlighted in the picture above, it mentions that Dout might ...
- 523
1 vote
1 answer
239 views
Is there metastability concern in the design of "slicer" part of serdes receiver circuit?
It seems that metastability is an important aspect of concerns when designing sequential circuits. This related to the fact that the signal must wade through the "forbidden zone" when it ...
- 523
3 votes
6 answers
1k views
Synchronization of handshake channel with different clock domains
My course on design of digital systems uses the book "Introduction to Asynchronous Circuit Design" by Jens Sparsø. On page 156 he talks about synchronizing a handshake protocol between a ...
- 4,776
1 vote
5 answers
267 views
Why would an intermediate voltage level cause a metastability in a SR-latch
Transistors and logic gates are actually analog in nature they aren't digital they don't turn on or off at certain voltages. Image source: All About Circuits - Voltage Tolerance of CMOS Gate Inputs ...
- 301
6 votes
2 answers
530 views
Understanding metastability in Technion Paper
I am trying to understand metastability as introduced in the Technion IEEE paper (link). But I am struggling a little with some of the concepts, and wanted to ask about that. This is the flip-flop ...
- 333
0 votes
2 answers
233 views
Shared FIFO control module between UART, PS/2 protocol, UART is ok, PS/2 has issue locking on to packets during read
I have brought over a design from a previously provided source in my FPGA. This is the FIFO controller for my system that gets instantiated in both UART sub system, as well as PS/2 sub system. The ...
- 181
3 votes
0 answers
166 views
D-type LATCH output when minimum clock/enable pulse width is violated and input/output are the same [closed]
Can the output of a D-type latch go metastable when: There is a minimum CLK/ENable pulse width violation The input and the output of the latch have the same value?
- 39
4 votes
2 answers
1k views
Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily". So, my question is: Why do almost all of ...
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