Questions tagged [artix-series-fpga]

Question 1

This is going to a very oversimplified post This is about interfacing a camera sensor to a fpga and I'm a newbie. Short question : I have this FPGA, and this camera, how do I interface them? Sub-...

Question 2

I have a design where an SPI CLK comes in on a non-CCIO pin. I can not change the pin. The FPGA is an Arty7. I am looking for ways to still drive sequential logic from this pin. I understand that this ...

Question 3

I would like to get an explanation or be directed to a specific literature to understand the behavior below. I am using Digilent NEXSYS-A7-100t with AMD Vivado and running post-implementation timing ...

Question 4

With the old Xilinx ISE/iMPACT tools one could connect to an FPGA via JTAG, and then select a menu option to read out the CRC from the programmed part. This was also useful from an engineering ...

Question 5

We are using Artix7 200T in our design. We are using two independent DDR3L (MT41K512M16VRP-107 AAT) interface in our card. Both with 8Gb capacity with 16 bit data width. Both DDR is completely ...

Question 6

This is the first time I use Vivado. I can't set test_mySWLED.v as Top I Run Behavioral Simulation End up with mySWLED waveform instead of test_mySWLED waveform. Here is my project: https://...

Question 7

I'm currently planning a setup as shown below, where I need to operate the GPIO on my chip at a data rate of 100 Mbps. My biggest concern is whether it is a feasible to drive LVCMOS12 on Xilinx Artix-...

Question 8

I am trying to run the LiteSATA bench file provided for the Nexys Video (Artix-7 xc7a200t-sbg484-1). The board is new and does not have anything connected to it, and I am building / loading the ...

Question 9

What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel. At first I was thinking of configuring on-board DDR ...

Question 10

There are 256MB DDR3L SDRAM installed on Digilent Arty A7 FPGA development board. Dual Channel memory is popular nowadays in a PC. So I was wondering if there is any chance to configure the DDR3L ...

Question 11

I want to implement the SPI controller for an ADC and have the following timing diagram : I'm implemented an FPGA controller that works on posedge clock, detecting the data coming from DOUT pin (it ...

Question 12

I am trying to generate images on a Samsung S22C300H monitor using the Diligent Nexys 7 board running the Xilinx Artix 7 FPGA. Even though the datasheet says the display supports 640x480, I was only ...

Question 13

I am a newbie to FPGA development. Any help will be highly appreciated and please forgive me in advance if the question is too obvious. The board is Chipwhisperer 305 artix-7 fpga. Used tool vivado ...

Question 14

I am trying to test the reliability of a circuit design on my FPGA board. (using Vivado, Artix-7 xc7a35tcsg-c board). The reliability here means the outputs of my circuit are expected to be persistent ...

Question 15

I'm new to FPGAs and I'm trying to determine how an FPGA determines whether to register an input as a logic 0 or 1. The FPGA I am using is the Artix 7 and I would like to connect it to a function ...

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Questions tagged [artix-series-fpga]

MIPI to SPI conversion doubt

Using a non-clock pin to drive sequential logic on Artix7

VHDL counter simulation abnormal start

In Vivado Hardware manager, how can I (either by menu option or TCL script) read back the CRC from a programmed Xlinx/AMD 7-Series FPGA

DDR with ARTIX 7 is not initialaizing

How to set a testbench file as top level entity ? [Vivado, Basys3Artix7]

Can I drive LVCMOS12 on Xilinx Artix-7 at 100 Mbps?

Artix-7 SATA implementation using LiteSATA won't initialize

Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?

Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?

FPGA SPI controller ADC + posedge/negedge constraints

Nexys 7 FPGA Verilog VGA signal recognized but nothing displayed

How to visualize the waveform of multiple clock domain-based signals in the vio and ila?

How to get the voltage or temperature within FPGA?

FPGA logic threshold - distinguishing a logic 0 and 1

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