Questions tagged [cdc]

Question 1

I know that asynchronous FIFO and handshake can do CDC, but the FIFO consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I ...

Question 2

I'm the newbie in FPGA. I want to design a frequency counter, so the design will involved some CDC problem. Therefore, I used FIFO (I use the Quartus FIFO IP) and 2DFF synchronizer in my design. Below ...

Question 3

Clock crossing FIFOs are essential components of multiple clock designs. I wish to understand, must they be built from Block RAM (i.e hard memory blocks) or they can also be built using registers? The ...

Question 4

I have seen designs for asynchronous resets synchronization like in this picture: I think I understand the asynchronous assertion and synchronous deassertion that this design delivers. I am not ...

Question 5

I-m trying to accomplish best USB speed through STM32H743 MCU to PC. First of all I was testing just receiving data. I was sending sending 8192 bytes from MCU to the pc without any other tasks, and ...

Question 6

There is a device. On board, STM32F446 + USB3315 as PHY + USB HUB assembled on USB2503. Frequency APB 180 MHz A device project with a CDC interface has been created in CUbeMX. On command from the host,...

Question 7

I have our old instrument which are showing flow over USB port using (Communication Device Class ASF Example). I am able to get data over UART 115200 using Teraterm. I want to have this data parsed ...

Question 8

My project needs to extract sensor data from STM32, now my problem is this CDC_TRANSMIT_FS function can only send uint8_t data, I want to at least send uint16_t data or 32-bit float, how can I achieve ...

Question 9

I am (re)designing an SPI slave module in VHDL for an ASIC. The SPI domain is faster than the main clock domain (~10MHz and ~1MHz), so the SPI state machine operates in the SPI domain. The previous ...

Question 10

I have an external ADC with a serial interface that has one data_out pin and CLK pin (16 MHz) the data_out pin transmit 16 bits of valid data then. An all-zero pattern follows the data after all valid ...

Question 11

Assume that within an FPGA, I have two data streams that are being driven by two clocks. The two clocks are generated by 2 physically separated PLLs (still within the same FPGA), both of which have ...

Question 12

There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use ...

Question 13

Given the below scenario, which is a reset-domain-crossing violation : Can it be resolved using some reset synchronization strategy? Is such design considered bad to begin with, i.e. need to avoid ...

Question 14

Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...

Question 15

In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...

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Questions tagged [cdc]

Can I do multi bit CDC using synchronizers without handshake or FIFO?

2DFF synchronizer output was determined to be a clock by timing analyzer

FPGA: Must clock crossing FIFO be made up of BRAM?

Is it possible to use a 2 flip-flop synchronizer for reset?

STM32 USB Full Speed and card reading causes slow USB speed

Increase USB HS transfer rate above 100 megabits

Need to read USB CDC data (UART over USB) from instrument using STM32F103C8T6 Blue Pill

STM32 USB virtual port data sending problem

Clock domain crossing without synchronisers

External ADC with SPI NUCLEO-H743ZI2

Do I need a clock crossing circuit for signals clocked by mirrored PLLs?

Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?

RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?

How to properly implement an n-FF synchronizer in Lattice FPGAs?

How to calculate the number of required flip-flop stages needed for clock-domain crossing?

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