Questions tagged [pci]

Question 1

I have a custom x8 PCIe card PCBA I am plugging into an x16 PCIe slot on an off-the-shelf motherboard. Would I be able to get the full 75W (5x 1.1A 12V and 1x 3A 3.3V) onto my x8 card? I am reading ...

Question 2

I was reading about the PCIe stadard, it was mentioned about PCIe PHY, Switched, RootComplex and Bridges that make the PCIe fabric. I'm trying to connect the dots between the physical hardware and the ...

Question 3

When PCI Express replaced the operation of reading directly from a PCI peripheral card over a bus, directly addressing its I/O ports, or performing a configuration cycle on it directly, with instead a ...

Question 4

If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster. But if you never need ...

Question 5

I need to add 32 serial ports to an SBC, for my tests I'm using a raspberry CM4, but it could also be a similar SBC. I'm trying to figure out what solution is best for having 32 serial ports on my ...

Question 6

If a PCI bus master can access memory space just as cpu can, can it put an address on the memory bus of the cpu that actually triggers a memory mapped I/O device to respond to that address. (As if the ...

Question 7

Does pci require routing mechanism in those 2 cases The two devices are on the same PCI bus and aren't seperated by a bridge. They aren't on the same PCI bus. I don't think it requires a routing ...

Question 8

I am new to PCIe. I would like to understand 256 (bus), 32 (device), 8 (function). I am trying to visualise these PCIe slots on a motherboard. I am used to desktop motherboards where we have one ...

Question 9

I have a question related to the PCI Express protocol. I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process. I know the ...

Question 10

According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)? If not, ...

Question 11

I'm trying to bringup PCIe, and stuck when trying to link up. Configuration Link Status is 00, which means "No receivers detected", as this document says ...

Question 12

In PCI bus introduction materials, especially when talking about the load capacity of the PCI bus, it's often stated that a PCI card inserted into the PCI slot is actually acting as two loads on the ...

Question 13

My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC? https://people.freebsd.org/~jhb/papers/bsdcan/2007/...

Question 14

This may well be a daft question and/or a failure to google effectively (and apologies if this would be a better fit on SuperUser or somewhere else?) but is it possible, in low-level hardware, to ...

Question 15

M.2 connector type (key B) support PCIe ×2, SATA, USB 2.0 and 3.0, audio, UIM, HSIC, SSIC, I2C and SMBus. I want to use SATA interface with my device, but I need to detect the reboot of the host ...

Stack Exchange Network

Questions tagged [pci]

75W over x8 slot PCIe

PCIe implementation

Origin and underlying sense of the term "Posted" in PCIe

Do extra PCIe lanes improve latency?

32 UART on a single system

Can a PCI bus master access a device mapped in cpu memory space

Does PCI require bus transaction routing

PCIe Domain, Bus, Device, Function limits

How are BAR registers handled between end points in PCI Express?

Remapping a PCI(e) device when another core is accessing the device

What does "No receivers detected" mean for Configuration Link Status?

Why is a PCI card treated as two loads on the PCI bus?

Do PCI Express devices' interrupts always go through a PIC or an APIC?

Detect power/run status of PC in hardware

PCIe PRST pin functionality at M.2 connector (B) with SATA device (reboot detection)

Hot Network Questions