BCD Counter False Start

Question

I am trying to implement a Digital Stopwatch in Xilinx ISE using four 4-bit Mod 10 BCD Counters and two 3-bit Mod 6 BCD Counters

They are cascaded in the following way:

4-bit --> 4-bit --> 4-bit --> 3-bit --> 4-bit --> 3-bit

RESET and CLK are the two global inputs. CLK is connected to BCD1 and its CLR is connected to the CLK of the next BCD. CLR gives 1 as long as 000 or 0000 is present.

Now when I test it, I am getting a false start, as CLR of BCD1 is already 1 and on the next falling edge, the first and second BCD both turn to 0001.

How can I get rid of the false start?

A very warm welcome to the site. Unfortunately, your question is missing a lot of information and cannot be answered as it is. Please edit it and show your source schematic or HDL. I imagine it's a schematic as you wouldn't need to section HDL into specific counters like you have. — TonyM
– TonyM, Commented Jun 13 at 15:52
When you reset all of the counters, aren't all five CLR outputs high? Are the counters synchronous or non-synchronous? Is the clock input level sensitive or edge sensitive? — AnalogKid
– AnalogKid, Commented Jun 13 at 16:34
The schematic symbol indicates that the counters increment on a positive edge, but you say it is on a "Falling Edge". Which is it? — AnalogKid
– AnalogKid, Commented Jun 13 at 16:37
@AnalogKid Yes, when the Counters output Low (0000 or 000) then CLR is high. The counters are Asynchronous. The Counters are connected using D-Flip Flops and the Counters increment on a Falling Edge and not a Positive Edge — EW3A
– EW3A, Commented Jun 13 at 16:49

Dave Tweed · Accepted Answer · 2025-06-13 19:12:21Z

It's clear that the CLR output is just a NOR gate on the counter outputs, and as such, it has glitches -- note that the "tens" counter advances when the "ones" goes from 0011 to 0100. This means that CLR can't be used directly as a clock. You need to find a different way to cascade your counters.

The real problem is that even if CLR were glitch-free, it wouldn't do what you want anyway — it makes a high-to-low transition when the counter counts from 0 to 1, which means that your clock would go 08, 09, 00, 11, 12, etc.

The traditional way to cascade ripple counters is to simply drive the next counter from the current counter's MSB directly. When it makes a high-to-low transition (i.e., 9 → 0 for the 4-bit counter, or 5 → 0 for the 3-bit counter), the next counter will increment cleanly.

AnalogKid · Accepted Answer · 2025-06-13 17:36:58Z

Dave makes an excellent point.

One solution is an R-C lowpass filter with a time constant of something like 500 us. This is 20x faster than the system clock frequency, and at least 500x slower than the metastable glitches. Unfortunately, you need five of these, one for each downstream clock input. If the system clock waveform is clean, the first counter does not need one.

I've done this in the past by bringing a signal out on one pin, through the external R-C, and back in on another pin. Unfortunately, this works for you only if your device has 10 available unused pins.

If there is a higher-speed clock available inside the device, it can be used with a counter and some gating to form an equivalent lowpass filter.

Dear god, no! This is just using a band-aid to cover up a problem that shouldn't have existed in the first place. — Dave Tweed
– Dave Tweed, Commented Jun 13 at 19:10
Seems a bit harsh. Whether or not the problem "should" exist, it actually does. I gave two real life solutions, both of which have been in production. I don't see a down-vote. — AnalogKid
– AnalogKid, Commented Jun 13 at 21:49
See my answer. Not only does hiding the glitch fail to fix the underlying design problem, there's a perfectly glitch-free solution free for the taking anyway. — Dave Tweed
– Dave Tweed, Commented Jun 13 at 22:26

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