1
\$\begingroup\$

I'm designing a mod-19 counter in Logisim using two 3-bit (mod-8) counters:

  • Counter A – low-order bits (0…7)
  • Counter B – high-order bits (0…2)

1 Asynchronous version (works)

  • Clock drives A directly.
  • B’s clock is A’s carry-out.
  • An asynchronous clear forces both counters to 000 when (B,A) = (2,2).

Expected / observed sequence

 00 01 … 07 10 11 … 17 20 21 22 → 00 01 …

enter image description here

Everything behaves as intended: at (2,2) the async clear fires and both counters jump to (0,0).

2 Synchronous version (misbehaves)

I wanted a synchronous reset, so I:

  • Enabled the LOAD pin on both counters.

Observed sequence

 … 17 20 21 22 → (2,3) → (0,2) → … → 22 → (2,3) → (0,2) → …

enter image description here

3 What I expected

  • Expected: (2,2) asserted ⇒ LOAD = 1 ⇒ on the next clock both counters load 000.

4 Question

What is the proper way to implement a synchronous reset in this two-stage counter so that the sequence ends cleanly at (2,2) and restarts at (0,0)?

Edit (delete if not relevant soon):

Quick follow-up on the ripple (fully asynchronous) version:

I tried using the CLR pins instead of LOAD.
I AND’ed the two comparators (B = 2, A = 2) and fed that straight to both CLR inputs.
But the counter still clears one count early: the sequence goes … (2,0) → (2,1) → CLR → (0,0).
I never see (2,2).

Schematic here if helpful: enter image description here

Here’s a concise EE.SE comment you can post—and the full state table you asked for. Just drop the comment under their answer, and update your question with the table.

State table for my asynchronous-reset version

counter-8¹ counter-8⁰ CLR₈¹ CLR₈⁰
0 0 0 0
0 1 0 0
0 2 0 0
0 3 0 0
0 4 0 0
0 5 0 0
0 6 0 0
0 7 0 0
1 0 0 0
1 1 0 0
1 2 0 0
1 3 0 0
1 4 0 0
1 5 0 0
1 6 0 0
1 7 0 0
2 0 0 0
2 1 0 0
2 2 1 1
\$\endgroup\$
2
  • \$\begingroup\$ @periblepsis Hi. Thanks for the concern. I’m actually trying to reason this out step-by-step. The screenshots show where I am stuck. If you see a flaw in the way I gate the enable/clock lines, could you point it out? That would help me think it through properly \$\endgroup\$ Commented Jul 13 at 17:54
  • \$\begingroup\$ @periblepsis Thanks, I appreciate you’re taking the time. Even if it feels obvious to you, I’m still learning how to align the enable/clock and load signals correctly. \$\endgroup\$ Commented Jul 13 at 18:01

1 Answer 1

Reset to default
3
\$\begingroup\$

Given that you must use those 3-bit counters and 3-bit comparators, as shown, and that this is to be a synchronous process then all you need to do is to lay out a very simple table. Just document the values for the load and ct inputs at each step:

$$\begin{array}{c|c|c} \text{Counters} & \text{counter-}8^1 & \text{counter-}8^0 \\\hline {\begin{smallmatrix}\begin{array}{c|c} 8^1&8^0\\\hline\\ 0 & 0\\ 0 & 1\\ 0 & 2\\ 0 & 3\\ 0 & 4\\ 0 & 5\\ 0 & 6\\ 0 & 7\\ 1 & 0\\ 1 & 1\\ 1 & 2\\ 1 & 3\\ 1 & 4\\ 1 & 5\\ 1 & 6\\ 1 & 7\\ 2 & 0\\ 2 & 1\\ 2 & 2 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{c|c} Load & Ct \\\hline\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&1\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&0\\ 0&1\\ 0&0\\ 0&0\\ 1&0 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{c|c} Load & Ct\\\hline\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 0&1\\ 1&0 \end{array}\end{smallmatrix}} \end{array}$$

The above is very easy to produce.

step 1 -- synchronous counters

enter image description here

I've disabled the asynchronous resets and supplied the desired load value of 0 to both counters. I've also included the synchronous clock.

Obvious first step.

step 2 -- comparators

enter image description here

The two counters must be reloaded is when the state is 2 2 and I've included that detail, above. (I've also added a way to watch the counter.)

step 3 -- load condition for both counters

enter image description here

Just AND the two comparator outputs to get the load condition for both counters. (This is obvious given the above table.)

step 4 -- ct condition for the low-order counter

enter image description here

Just invert the above load output to get the ct condition for the low-order counter. This is also obvious from a very simple inspection of the \$8^0\$ column.

step 5 -- ct condition for the high-order counter

enter image description here

The carry-out of the low-order counter must be AND'd with the above ct condition of the low-order counter in order to get the ct condition for the high-order counter. This is because you want the carry-out of the low-order counter except when you are in the business of performing the counter-load-operation at the end of the counting sequence.

done

That's it. The process always starts with a table of some kind. That will be the guide for the rest. Please make sure to include such a table when asking questions like this. It's a first and necessary step.

\$\endgroup\$
18
  • \$\begingroup\$ can i ask what do you use to draw the circuits ? \$\endgroup\$ Commented Jul 13 at 20:11
  • 1
    \$\begingroup\$ and this was really fun to read thanks \$\endgroup\$ Commented Jul 13 at 20:12
  • \$\begingroup\$ @dareen Thanks for the kind words. :) And I used Logisim. Aren't you using Logisim? \$\endgroup\$ Commented Jul 13 at 21:15
  • 1
    \$\begingroup\$ @Pato Well, of course it clears early. I used 2 and 2 plus the AND gate to generate an output of 1 when that state occurs. But this will clear the counters just as they go to state 2 2. The fix is glitchy, of course. But if you want to use the asynchronous clear then you need to look for 2 3, instead. That will only happen on the following rising clock edge (not good but that's what you have to do) -- forcing both counters to 0 0 quickly. This means there will be a very very short period while at 2 3 that almost instantly goes to 0 0. Ugly. Which is why synchronous is better. \$\endgroup\$ Commented Jul 13 at 22:13
  • 1
    \$\begingroup\$ @Pato I'm very happy that you seem to have followed this very well and can see the differences so clearly. And I'm glad to have had the chance to meet you this way. I think you will do well! Best wishes! \$\endgroup\$ Commented Jul 13 at 22:22

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.