I have several peripherals that connect to CPLD. They all have different propagation delays, and to compensate that I wish to introduce about 10-15ns delay into the CPLD logic. In detail, clkOUT should be lagging the clkIN by about 10ns. Is it possible to achieve by describing a behavioral model in VHDL? Any suggestions? clkIN = 10MHz.
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2 Answers
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4 No, asyncrhonous delays are not synthesizable constructs in an HDL.
However, if you don't require a lot of accuracy, you can artificially specify a long string of gates (e.g., inverters or buffers) and then use synthesis constraints to prevent them from being optimized away.
- \$\begingroup\$ Is it possible to impose synthesis constrains only on separate lines in the code, or they will apply to the whole model? \$\endgroup\$Nazar– Nazar2014-07-22 15:16:35 +00:00Commented Jul 22, 2014 at 15:16
- 1\$\begingroup\$ Constraints are not usually based on "lines of code", but rather specific signals. You attach the "keep" property to each of the signals between the gates. \$\endgroup\$Dave Tweed– Dave Tweed2014-07-22 15:27:48 +00:00Commented Jul 22, 2014 at 15:27
- 1\$\begingroup\$ if you have spare pins you can daisy chain through in and out buffers. It should give you more delay for fewer elements in your CoolRunner II. Unique pin names gives you a granularity of one buffer instead of two inverters. \$\endgroup\$user8352– user83522014-07-22 22:27:56 +00:00Commented Jul 22, 2014 at 22:27
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1 Dave Tweed's answer is correct, although I noticed that the solution you found on the Xilinx forums required you to use extra output pins on tri-state gates to prevent synthesis from removing your intermediary gates. For such a small change, you can use the Xilinx FPGA Editor to manually manipulate the synthesized design. You can find a tutorial here.
I'm unsure of what kind of resources that you have available in your CPLD (I typically work with large full featured FPGAs) but you could also use an MMCM/PLL or the like to re-generate an output clock with a certain phase offset (sub-1-cycle delay).
- \$\begingroup\$ Interesting. It will take some time before I understand how to properly use it. \$\endgroup\$Nazar– Nazar2014-10-30 19:38:35 +00:00Commented Oct 30, 2014 at 19:38