Questions tagged [programmable-logic]

Question 1

I am searching a solution about TYN612 thyristor base switching in automation. My logic is: If I made code to clear MCU PIN - 1 (PNP point) (digitalWrite(PIN, LOW);...

Question 2

I am currently working on a redesign of one of my older PCBs. On this PCB there is a HEF4046BT used as a PLL. I needed to exchange the CPLD, which is used as a frequency divider between the ports ...

Question 3

I’m working on a video pipeline where the source is an NVIDIA Jetson Orin Nano module. The HDMI output from the Jetson only supports progressive video modes (such as 720p or 1080p), and I need to ...

Question 4

How can I program this IC? There is almost nothing on the internet and everything is about PAL and GAL. Of course, it is said that all of these are similar, but the above IC is programmed differently ...

Question 5

I am embarking on a new project to replace simple scanning circuits. Previously this was done with a couple of 8 bit counters linked by glue logic, then driving multiplying DACs and other analog ...

Question 6

I'd like to use an 16CV8 or 20CV10 or some similar low-complexity erasable device for glue logic in a design. I know that they are quite elderly (I used one back in 1991, right after electrons were ...

Question 7

I have managed to implement the internal oscillator in the CPLD MAX II: EPM240T100C5. From what I can see it can be set to either I have used the wizard to generate the code for 5.56 MHz. The files ...

Question 8

I have a PCB with the a Xilinx CPLD and the TDI, TDO, TCK, TMS pins close to the JTAG programming header (2.54mm) have ESD suppressors (BZA868AVL). What is the purspose of these diodes on these pins?

Question 9

I have this very simple VHDL code that should implement a flip-flop with asynchronous (active low) Set and Reset. The clock (Clk) has no oscillator connected to the pin, only an input I can toggle ...

Question 10

I'm trying to design a 2 channel pwm generator with complementaries, duty cycle and frequency is adjustable, deadtime is adjustable, phase between two channels is continuously adjustable. I'd like to ...

Question 11

I am trying to get a 7-segment display to run off of an EFR32MG24 dev kit. I know the problem lies in the code, likely in the hex masks or the indexing. For troubleshooting, I have tried to adjust the ...

Question 12

I have this diagram from my class of how 3 6-input LUTs are used to create a Full 4-bit adder. It's not particularly clear, but each 6-input LUT has 2 outputs (so I suppose they're really operating as ...

Question 13

The features clause in the datasheet (https://www.microchip.com/en-us/product/atf16lv8c) specifically mentions "Inputs are 5V Tolerant", but the DC characteristics specify VIH to be MAX Vcc+...

Question 14

I am building an accessory for a 6502-based computer, and am trying to stick with (reasonably) period-era components. To this end I am using a GAL16v8 (specifically an ATF16V8C) to handle register ...

Question 15

When considering speed I have learned that PLAs are much slower than PALs. As each signal has to propagate through same sequence of gates (in series) why there is a speed difference?

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Questions tagged [programmable-logic]

How to made an automation TYN612 thyristor base switch

PLL not locking after CPLD change

How can I convert a progressive HDMI signal (e.g., 720x576p) to an interlaced PAL (576i) output using external hardware?

AMD PALCE16V8H-25 PC/4 programming

Which family of FPGA to choose [closed]

How do you program PLAs such as 20CV10, 16CV8, etc.?

Quartus internal oscillator

JTAG Programming Header - ESD suppressors

Different implementation between FPGA and CPLD?

Which logic device should I use? FPGA or CPLD?

Running a 7-segment display off of a EFR32MG24 dev kit, only segment A turns on

How would a 4-bit full-adder be implemented in a Cyclone V FPGA?

5V input tolerance on ATF16LV8

Trying to minimize product terms for GAL16V8

Why do PALs have higher speed than PLAs?

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