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I recently designed a passive RL ladder filter to obtain certain specifications for anti-aliasing purposes (circuit shown below and simulated in LTSpice). The response I got in LTSpice was very satisfactory.

Circuit

Simulated filter enter image description here

After constructing on breadboard I measured the response by doing a frequency sweep with persist on in FFT mode on a digital oscilloscope. The response was not at all as expected from the simulation. The cut off frequency measured in the circuit was much higher firstly. This I partly expected due to use of inductors (20% tolerance) and ceramic capacitors (10% tolerance). What I was not expecting was the massive ripple in the pass band region. There was about a 7dB difference between the tallest peak and the trough whereas in simulation the ripple was tiny. The filter ended up being sufficient to stop anti-aliasing (the stop-band attenuation was more important than the cut off frequency for my purposes) and I didn't bother to change it. I'm just wondering if anybody might know what went wrong or maybe on best practice for building RL ladder filters? In general if something works in simulation I expect at least semi-resemblance in practicality so I'd like to know what may have gone wrong for future purposes. What might cause such bad ripple in an RL ladder filter?

Physical response

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  • \$\begingroup\$ It comes down to specs for cost and tolerances. High Q 10% vs low Q with more stages vs 5% It depends on your specs and temp range. SNR in, out SNR after ADC and image distortion. Data jitter from group delay (ISI) it is best to use Raised cosine \$\endgroup\$ Commented May 29, 2019 at 14:22
  • \$\begingroup\$ What is your sweeping rate? That's going to strongly affect the measurement \$\endgroup\$ Commented May 29, 2019 at 14:50
  • \$\begingroup\$ @Blargian could you show your spice circuit? I simulate the same circuit above but the stop band is -100dB lower at 400kHz. Could you also look at a wider range like 4kHz to 4MHz? the passband does not look flat to me. A flat passband is very desirable in ADC applications, what exactly is this filter for? \$\endgroup\$ Commented May 29, 2019 at 16:18

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There was about a 7dB difference between the tallest peak and the trough whereas in simulation the ripple was tiny.

I see 5 to 5.5 dB ripple in your simulation graph (if I read it correctly) and it only goes down to 0.4 MHz so obtaining a real result that is 7 dB isn't that far off what you designed: -

enter image description here

Given capacitor and inductor tolerances plus inductor cross-talk possibilities, I would say you got what you designed. 2 dB is about a 26 % error.

However, you appear to have got your values wrong on your circuit - I would suggest that all the capacitors are in pF - C3n and C1n being quoted in nF is plainly wrong. Maybe this is also part of the problem because the ripple would be significantly less with the values in pF rather than in nF (as shown).

This is what you would get with what I assume to be the right values for C1n and C3n: -

enter image description here

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