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I made a circuit to convert 3,3 V to 1,65 V JTAG signals with SN74LVC2G125 buffer. I am using this circuit to program and debug an RF430 chip with a MSP-FET430UIF. I did the same circuit as page 32 SLAU607C from Texas Instruments.enter image description here The signals from the debugger (SV2 on the schematic) are good. However the NRST_IN and TDO signals are not good on the SN74LVC2G125 ouput (IC6 on the schematic). Their voltage is 2.7 V whereas I expected 3.3 V signals. The other voltages are good (FET_VCC=3.3 V as expected ; TDO from the chip (pin 7 on IC6) is 1.65V and RST/NMI=1.65 V as expected ; TCK, TMS and TDI on the SN74LVC2G125 ouput are 1.65 V signals). SN74LVC2G125 is powered with 1.65 V. I don't know where the issue comes from. Any suggestions ?

Thank you for your help,

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  • \$\begingroup\$ Well, they're basically "open collector/drain" outputs and could be loaded by circuits on SV2. 2.7 volts doesn't seem all that bad though. Maybe explain why you think 2.7 volts will be problematic? \$\endgroup\$ Commented Dec 18, 2020 at 14:37
  • \$\begingroup\$ If FET_VCC is 3.3v while IC6G1 and 2 are active, then whatever else is connected to TDO and NRST_IN must be loading it down. Either reduce the load, parallel more SN74's, or use a driver with higher current output rating. \$\endgroup\$ Commented Dec 18, 2020 at 15:16

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Reset to default
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Finally, the 2.7 volts was not problematic. The issue came from the debugger: with a newer MSP-FET430UIF bebugger the issue was solved.

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