I'm doing a preliminary FPGA design where I want to establish whether I will be able to implement the pinout and clock routing -- basically I'm placing all the hard IP blocks and wiring up the clocks, but I'd like to add as little other logic as I can get away with at the moment.
The optimizer now very aggressively removes a lot of logic due to the undefined signals, and associated clocks and hard IP as well, which makes life a bit more difficult.
In previous designs, I've simply routed undefined inputs and outputs to pins, which forced the optimizer to leave them in, but this time I'm out of pins already.
I'd possibly construct a massive shift register and connect that to some pins, that would likely tell the optimizer that the values of those signals are unknown but defined -- is there a better way to implement "placeholder" logic?
The goal right now would be to lock down a resource plan, which would allow board design to begin as soon as it is clear whether external clock routing and buffers are necessary and pinout is finalized.
