VHDL near text "begin"; expecting "end" Error

Question

I'm trying to learn VHDL and and trying to create an 8 bit 4 to 1 MUX. Below is my code:

LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE inputarray_type IS TYPE inputarray IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0); END PACKAGE inputarray_type; USE work.inputarray_type.all; ENTITY bit8mux4to1 IS PORT (inputs : IN inputarray;--ARRAY (3 DOWNTO 0) of STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END bit8mux4to1; ARCHITECTURE structure OF bit8mux4to1 IS COMPONENT mux4to1 PORT(i0, input1, i2, i3, s0, s1 : IN STD_LOGIC; output : OUT STD_LOGIC); BEGIN generate_mux: FOR i IN 0 TO 7 GENERATE stage0: mux4to1 PORT MAP (inputs(0)(i), inputs(1)(i), inputs(2)(i), inputs(3)(i), s(0), s(1), output(i)); END GENERATE generate_mux; END structure ;

The component mux4to1 works, and I've used it as a component in other code.

When I try to compile the code I get an error saying

"VHDL syntax error at bit8mux4to1.vhd(21) near text "BEGIN"; expecting "end"

I've tried changing the generate statement many ways and have tried commenting every line of the generate statement completely, but the error won't go away. What is the problem? Is there something wrong with the architecture?

You're missing an end component; before the architecture BEGIN. Maybe a copy of the standard or at least the syntax BNF would come in handy? — user16145658
– user16145658, Commented Sep 19, 2021 at 8:26
@user16145658 the text of your comment, perhaps with a link to said standard/grammar, would make a perfect answer. — TypeIA
– TypeIA, Commented Sep 19, 2021 at 13:09

toolic · Accepted Answer · 2021-10-14 12:56:53Z

There are two errors:

The lack of an END COMPONENT stanza
VHDL only allows one object per file; if you want more than one object in the same file, you need to repeat the LIBRARY stanza, it behaves as a completely new logical file.

Corrected code (verified with Synplify Pro):

LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE inputarray_type IS TYPE inputarray IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0); END PACKAGE inputarray_type; -- Different logical file below LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.inputarray_type.all; ENTITY bit8mux4to1 IS PORT (inputs : IN inputarray;--ARRAY (3 DOWNTO 0) of STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END bit8mux4to1; ARCHITECTURE structure OF bit8mux4to1 IS COMPONENT mux4to1 PORT(i0, input1, i2, i3, s0, s1 : IN STD_LOGIC; output : OUT STD_LOGIC); END COMPONENT; BEGIN generate_mux: FOR i IN 0 TO 7 GENERATE stage0: mux4to1 PORT MAP (inputs(0)(i), inputs(1)(i), inputs(2)(i), inputs(3)(i), s(0), s(1), output(i)); END GENERATE generate_mux; END structure ;

Your point 2. is incorrect factually. A design file is comprised of any number of design units. Design units are stored in a working library as the result of successful analysis. A primary and secondary design unit share a root declarative region. An optional context clause is part of some primary and secondary design units, preceding their declarations. An object is a value of a type. IEEE Std 1076-2008 13. Design units and their analysis, 12.1 Declarative region, 6.4 Object. Here the package declaration and following entity are both primary units and don't share a declarative region. — user16145658
– user16145658, Commented Mar 8, 2022 at 2:23
In English, stanza refers to poetic meter while the VHDL standard requires syntax specifies in a modified Backus Naur Form defined structure. The end component is required by the BNF defined in the standard see 6.8 Component declarations. Your code indeed analyzes and the design units package declaration inputarray_type, entity bit8mux4to1 and architecture structure are stored into the working library. You have the right answer, just not well articulated as to why it is correct. — user16145658
– user16145658, Commented Mar 8, 2022 at 2:31

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