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I designed a carrier board that has a Type6 COME module that outputs DisplayPort 2.1 to a Altera 5CGXFC7D6F27I7N Cyclone V FPGA. The FPGA firmware contains DisplayPort IP.

I am having problems getting the FPGA to detect the DisplayPort video. The PCB traces are about 3.5 inches long and the 100 nF capacitors are size 0201.

Does the circuitry below seem correct.

I thought it might be a BIOS setup problem but, in our COME developing board, it is able to detect the display port signals. I also wanted to add that I added a mDP connector on my carrier (the COME has 2 DP connections) that is working fine when I connect it to a monitor.

Below is my AUX circuitry. Does the implementation seems right?

AUX signal schematic going to the FPGA

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    \$\begingroup\$ What did the eye diagram look like? \$\endgroup\$ Commented Jul 18, 2024 at 20:35
  • \$\begingroup\$ I never scoped it. I will review it. \$\endgroup\$ Commented Jul 19, 2024 at 17:01
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    \$\begingroup\$ Can you show the layout? \$\endgroup\$ Commented Jul 23, 2024 at 13:43

1 Answer 1

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The issue ending up being the Altera IP block that we were using on the FPGA. It was not set to handle our purpose/use. Recommend you check/review that the IP you are using is set correctly.

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