Questions tagged [cyclone]

Question 1

I have a CycloneIV, which has an active-low /CE pin, and I'm wondering if that pin takes part in power up. It makes sense to me for a part that needs to be kept in reset until power is stable to have ...

Question 2

I'm using a CycloneIV E, and would like to have both JTAG and AS flash programming options available. Do I need two headers, like Figure 8-28 suggests, or can these be combined, as the pins used for ...

Question 3

What would be the easiest way to create a reset signal after new configuration has been downloaded to an FPGA? I've always done a reset manually via a switch .. but there has to be a better way - ...

Question 4

I have this diagram from my class of how 3 6-input LUTs are used to create a Full 4-bit adder. It's not particularly clear, but each 6-input LUT has 2 outputs (so I suppose they're really operating as ...

Question 5

Im working in a project with A FPGA board (De1-Soc - Cyclone V) and in project there is supposed to be an internal memory to make connection with rest of the system and read or write some data in it. ...

Question 6

I designed a carrier board that has a Type6 COME module that outputs DisplayPort 2.1 to a Altera 5CGXFC7D6F27I7N Cyclone V FPGA. The FPGA firmware contains DisplayPort IP. I am having problems getting ...

Question 7

I am currently designing a power supply setup for a Cyclone 5 FPGA. In the datasheet, it is stated that if power supplies do not reach operating conditions within the maximum tRAMP time allowed (100ms ...

Question 8

I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal. When I run in jtag mode it works, for ...

Question 9

So I am trying to use the LCD on the cyclone III FPGA. I have written this verilog code that should display numbers 0 to 9 then letters A to G Compiling the code has no errors at all However, when ...

Question 10

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...

Question 11

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...

Question 12

Problem I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...

Question 13

Considering these settings: Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV) IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V) Voltage between 0.8V and 1.7V on this input No CLK ...

Question 14

I have been building a synchronized I2C slave receiver with Verilog. The I2C slave receiver did not encounter any issues when I simulated it with Modelsim. However, it does not function properly ...

Question 15

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...

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Questions tagged [cyclone]

Chip Enable on Altera CycloneIV and power sequencing

Can I combine AS and JTAG headers for CycloneIV?

FPGA Reset Circuit after Download

How would a 4-bit full-adder be implemented in a Cyclone V FPGA?

Making memory in FPGA and how to use the SDRAM on De1-Soc board

DisplayPort video into a Cyclone V FPGA

When does the tRAMP timing begin for Cyclone 5 Power Supplies?

Assistance Needed: Trouble Running Bare-Metal Code on second core in Cyclone V SoC

Cyclone III FPGA 16x2 LCD repeat one character instead of displaying complete word

Debuging verilog SDRAM controller

Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"

Intel FPGA input voltage between Vil and Vih : what's happening?

FPGA counter value unstabillity

FPGA starts working after irrelevant changes, why?

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