1
\$\begingroup\$

I am trying to write to the SSD1306 OLED using Verilog on an FPGA.

I have simulated the following waveform which should clock out hex AF to the SSD1306 in the correct format:

i2c-$AF

The sck line has a period of around 2.5/2.6 microseconds from low-to-low/high-to-high.

The sda line changes state roughly at midway through the sck low state.

Here is the timing diagram from the docs:

timings

There are also some more relevant timings on page 21.

Did I miss something? New to I2C. So just trying to gain some fundamentals. I am a little unclear on the stop condition - do I have to pull sda from high-to-low back to high again just to stop?

-EDIT-

Hopefully this is the correct version!

correction

\$\endgroup\$
1
  • 1
    \$\begingroup\$ It might be worth trying to get the I2C gateware working with a much simpler device... that you can use and immediately determine if the I2C transaction is valid - for example a basic I/O expander. \$\endgroup\$ Commented Jan 13 at 22:06

2 Answers 2

Reset to default
1
\$\begingroup\$

No it does not write to the chip.

The protocol, both in bit level, byte level and transaction level are incorrect.

First of all, there is no I2C address of the target chip sent out, only the 0xFA byte, which is not a write to SSD1306, it's an address write to some other chip with a command to start reading from it - with no data clocked out.

If the clock period is 2.5 us, the duty cycle cannot be 1.25 us high and 1.25 us low. Assuming signals are ideal and there is no delays from rise or fall time, clock must be low for 900ns and high for 1600ns, meaning, allowing for 300ns rise and fall times in the transitions, the low time can be 600ns and high time can be 130ns.

A basic transaction is:

  1. start
  2. chip address
  3. bytes to chip in the way it wants them, like in this case, control bytes following data bytes
  4. stop

The electrical interface must be open-drain, so it will not work if push-pull outputs are used.

There are very good app notes about fundamentals of I2C, if the actual standard is too complex.

\$\endgroup\$
2
  • \$\begingroup\$ Got it! Thanks. Questions: what is a ‘duty cycle’? What does it mean ‘open drain’? \$\endgroup\$ Commented Jan 14 at 1:24
  • 1
    \$\begingroup\$ @K_T I think they have been asked here before, and even if not, it would be faster for you to read about these terms from Wikipedia or with your favourite search engine. \$\endgroup\$ Commented Jan 14 at 5:31
1
\$\begingroup\$

do I have to pull sda from high-to-low back to high again just to stop?

Yes, section 8.1.5.2 Write mode for I2C of the data sheet says:

The stop condition is also defined in Figure 8-8. The stop condition is established by pulling the “SDA in” from LOW to HIGH while the “SCL” stays HIGH.

Figure 13-5 in your question also shows SDA=0 during the last low-to-high SCL transition.

Refer also to Figure 8-8: Definition of the Start and Stop Condition

Many of the timing figures are from the I2C user guide.

The waveforms at the bottom of the question look better. You need to make sure you satisfy the "Stop condition Setup Time" (minimum 0.6us).

\$\endgroup\$
0

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.