Controlling 7-Segment Display

There is a bit of a substantial learning process needed to get to the end-point of functional and fully programmed CPLDs and FPGAs on a board that you can use for your project. Starting from where you appear to be that path is already long enough, let alone further learning barriers some packages may make manifest as you get closer to building something.

You are also toying with the idea of using existing binary (or decade, as has been recommended in comments) counters and possibly an adder. I'd like to help make you more aware of another approach, so that you can compare it with what you are currently considering.

The following is only an answer in so far as it may expose an approach that may fit within the limits you've discussed. But it's not a complete answer.

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Suppose you had 9 control wires that needed to be sequenced in 4 steps, like this:

$$\begin{matrix} 8&7&6&5&4&3&2&1&0 \\\hline 0&1&1&1&1&1&0&1&1 \\ 0&0&0&0&1&0&1&1&0 \\ 0&0&0&0&1&0&0&0&1 \\ 1&1&0&0&0&0&1&0&1 \end{matrix}$$

That can be achieved in a number of ways. But there is a long-since standardized way of using AND/OR and JK FFs, which I'd like to show using the above simple state machine that moves through four states and starts over again.

(The process is very general and was partially achieved using PAL and PLA devices in the 1980s, and after.)

The idea is so simple that I took only 90 minutes to write up the following program to demonstrate it. (I took the time as I have a different use in another project. For now, its output isn't very polished.)

The binary for the control wires (and their decimal equivalents) are on the left side. But as FFs can often be more readily power-on reset to a state of zero, these values are modified and compressed into the four states shown under States. It always starts with 0 as the first state!

Underneath FF Outputs is listed all of the output wires and how they are taken from the JK FFs, showing whether to use the \$Q\$ or \$\overline{Q}\$, as well.

Implementing this in logic creates the following synchronous state machine:

(I used Neemann's DIGITAL program for the above image and to process the output table that my program produced on the right-hand side in CSV format.)

And that's it.

Here are the four states, in operation:

You can see that the outputs at each state are exactly as expected from the initial table. (On the next clock, after State 3 above, it will return to State 0.)

The idea can be used to also make up an arbitrary state machine that would directly drive the 7-segment displays, for example, without actually involving any binary or BCD formatting. It would directly control the individual LED segments in a stepped sequence.

It could not only do that, but it could also simultaneously generate any arbitrary set of control wires for any purpose you wanted. Including a special control wire to block the count-down when at 250 and block the count-up when at 390, for example.

Although I don't show it in the above example, the 90 minutes I spent coding the above program also can handle states that have the same value but exist elsewhere in the state machine sequence. It knows how to generate JK FFs when needed for such cases.

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If you provide more details about how all this gets used and if I can see my way clear to writing more, I may try. But I have to stop here, given the limits of what I think I understand.

(Also feel free to ask questions about how one moves from a set of desired sequential states to a synchronous system implementing those states. It's not complicated and easy to explain, if you are interested in the process. What I've provided is more Moore than Mealy. But Mealy is also very interesting and not much different except in one specific detail. I can provide references to papers I believe may help, if desired.)

appendix

Here's a process that might be followed to develop the above state machine device:

The table in the lower-left corner identifies which of the JK FFs may be used to drive any specific J or K. This machine only had a few states, so it was much more likely than not to find outputs that would work as inputs. So no logic was required in this case.

For longer state sequences, it is much more likely that some logic will have to be added to the state outputs to get specific J and K sequencies. There are handy tools that can help find the right logic for these cases.

But the upshot is that if you use AND gates with as many inputs as there are JK FFs and if you follow that with OR gates, then you can implement any SOP expression needed. This is a very general approach that always works and was the basis for the importance of PALs and PLAs back in the day.

addendum

The number of JK FFs can be further reduced to just two. Since there are only four states, intuition might suggest further investigation into this idea.

As it turns out you can find that \$Q_0=\overline{Q_1} \wedge Q_2\$, \$Q_3=Q_1\vee Q_2\$, \$Q_4=Q_1\wedge Q_2\$, and \$Q_5=Q_1 \oplus Q_2\$. Since in all these cases only two JK FFs are required for the equations, four of the JK FFs can indeed be removed in exchange for some logic:

I've re-arranged the FFs in both of the above cases so that the right-most two JK FFs are arranged as a simple binary counter pair -- identical to each other in that respect. What the remaining four JK FFs do in the top case is handle the otherwise-required logic gates. There's four states, either way, of course.

What I used to do in the 1970's is look at the excess gates I had available (because I was using 7400 series logic packages) and make choices based on what required the fewer packages in total. In the 1980's and later, there were PALs, PLAs, CPLDs, FPGAs or ASICs (when working with a team having access to such things) and considerations would of course be different for those cases.

Hopefully, this expands your thoughts on the topic and that you can find an optimal arrangement for your specific case. Or stick with your own prior approach, if that works better for you.