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4 layer board. V+/- enter at one end. I've got space along the back edge for pours forming a shared supply bus for multiple loads.

Loads are all SMPS with fairly stiff transients. V+ goes in on the top with input filters, great.

But on the bottom, they each have a high di/dt power return (PGND) next to an analog return (AGND) that needs to be relatively quiet. That might be okay if they didn't all need to branch off the same bus (space is limited). The transients are all synchronized, so that's good and bad.

(To clarify, the top edge of the board is all I have to work with. The loads are all isolated -- think multi-rail isolated POE injector.)

Problem is that the ground wants to ring like a bell in the MHz range (switching at 250kHz) on my design using layer 2-4 as a big shared ground bus. I realize that I've probably overdone it -- decreased loop inductance and increased capacitance to the point that every transient and stray emission is excellently coupled to all my grounds. Also, it seems less than ideal to have the switching currents of all the downstream devices travel (most directly) through the copper of the upstream AGNDs. So I'm going back to the drawing board.

Not asking anyone to design this for me, so I'm keeping it general. I've been banging my head on the wall trying to get these return/grounds quiet. Faced with this situation, have any thoughts on best practices?

Here's a general idea of the layout, as well as some ideas I had. (Slotting the pours, selective vias to a buried PGND, any others?)

For example:

Each of the AGND/PGND load return need to be tightly coupled per device. Normally, I would do that with a star ground. Obviously, they all share this long bus, and I don't have room to run a bunch of separate return traces down this strip of board.

Now, I could be wrong, BUT. My assumption is that I need a ground plane on layer 2, just under the V+ pour (layer 1), to reduce the V+ inductance. This doesn't have to be connected to the noisy power returns, but could go back to the main 0V to act simply as a shield and inductance-reducing return path, leaving layer 4 for PGND and AGND. I could let them both return to the bus at the same point, and maybe even slot the bus to prevent downstream currents from running across them?

Or I could treat layer 2 as primarily PGND, drop vias right at the load power returns down to layer 2, and try to shunt the biggest portion of the current transients to the "noisy" layer 2 ground, while trying to solely maintain the layer 4 copper for a good AGND/PGND bond and more AGND-focused return.

Thank you, Giordy

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  • \$\begingroup\$ You haven't described what problems are being faced nor how you measure the ringing. I mean; it could all be scope probing artefacts and an engineering belief system that is flawed that drives you down the path of fixing something that works so, does the current design work or does it give you problems. If "problems" then what are they? \$\endgroup\$ Commented Nov 18 at 12:28
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    \$\begingroup\$ A full board shared GND often does work even with switchers if other stuff is done right, so it would depend. do you have any more detail you can share (schematic / layout)? \$\endgroup\$ Commented Nov 18 at 13:15
  • \$\begingroup\$ @Andyaka, thanks for your comment. I'm probing with a ground spring. On-time and off-time switching transients are causing ringing on the ground planes at around 100MHz, with enough amplitude to falsely trip over-current at idle. There was less noise when it was a 2 layer board -- there was still ground noise, but it was at most 1/5th of what I'm seeing with 2 inner layers dedicated to ground and bonded together with vias. This would suggest the decrease in inductance and increase in capacitance are at fault. So I'm looking for guidance on the best ways to move the copper in a system like this \$\endgroup\$ Commented Nov 18 at 18:04
  • \$\begingroup\$ Anybody have any more questions or thoughts? I'm getting desperate, my whole life may be riding on solving this problem. \$\endgroup\$ Commented Nov 19 at 3:53

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To treat ringing on power, consider common mode chokes (lossy ones) on power/power ground pairs. That would damp ringing, and doesn't disturb the analog GND.

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  • \$\begingroup\$ Thanks for the input. That does make sense. This design actually worked much better when it was a 2 layer board, before I added the inner layers of ground pour. I believe I can get performance to an acceptable level simply by manipulating the copper, given the right stackup and layout. \$\endgroup\$ Commented Nov 18 at 6:41
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    \$\begingroup\$ @Giordino , that's an interesting clue as well, if the problem appeared after adding layers \$\endgroup\$ Commented Nov 18 at 13:16
  • \$\begingroup\$ @PeteW, I thought so as well. I think that's the critical data point. So, if I can get the best of both worlds (the reasonably good 2 layer, and a helpful application of the 2 added inner layers), that would be ideal. I think the answer is probably simple, it just eludes me. The real solution may be to print a few boards with different ground pour arrangements and try it out. But I'll wait for the guidance of the group here. \$\endgroup\$ Commented Nov 18 at 17:56

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