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Questions tagged [verilog]

1 vote
0 answers
24 views

This question was ported over from here: I am using the following command line to run the auto processing on a verilog file: emacs -batch file.v -f verilog-batch-auto; When I get the error, it is not ...
Nazar's user avatar
  • 111
0 votes
1 answer
177 views

I have 1 top module and 1 submodule and i want to autoinst using auto template and regex, my modules are:- module submodule ( input [31:0] in_data, input in_valid, ...
Avik Sarkar's user avatar
0 votes
3 answers
836 views

I am using verilog mode for Emacs. I am trying to find which begin is paired with which end. Is there any way to do this in Emacs?
Roarer's user avatar
  • 11
2 votes
2 answers
696 views

When I use the Verilog Mode in spacemacs with evil keybindings, every time I type e.g. wire and press ESC, an automatic dialouge pops up and asks me msb:, lsb: and name (RET to end). This is super ...
Jounathaen's user avatar
2 votes
1 answer
797 views

The verilog-mode package contains this code: (define-skeleton verilog-sk-header-tmpl "Insert a comment block containing the module title, author, etc." "[Description]: " "// ...
adrianf0's user avatar
4 votes
2 answers
775 views

I am using outshine to organize my code (verilog/systemverilog language). Here is an example use: // * Class definition class my_class extends my_base_class; // code .. // ** Task 1 ...
Kaushal Modi's user avatar
  • 26.4k
7 votes
4 answers
827 views

In Verilog/C/C++, comments can begin with //. Here's an example comment, //This is a comment I like to use the find-file-at-point feature. If my cursor is on the file name in `include "some_file.v". ...
Kaushal Modi's user avatar
  • 26.4k