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Fix simpleuart baud rate calculation#162

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anishathalye wants to merge 1 commit intoYosysHQ:mainfrom
anishathalye:simpleuart-baud
Open

Fix simpleuart baud rate calculation#162
anishathalye wants to merge 1 commit intoYosysHQ:mainfrom
anishathalye:simpleuart-baud

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@anishathalye anishathalye commented May 2, 2020

This patch fixes the baud rate calculation so that the behavior of simpleuart is in line with the description in picosoc/README.md:

The UART Clock Divider Register must be set to the system clock frequency divided by the baud rate.

Previously, the effective behavior of simpleuart was

divisor = (clock frequency / baud rate) - 2 

The fix is done basically by comparing *_divcnt + 1 >= cfg_divider instead of the old *_divcnt > cfg_divider. A special case is needed in the receive logic for the case where the divider is equal to 1, where at the next cycle we want to read the first bit (jumping straight to a recv_state of 2).

This patch also makes some minor stylistic changes that fix Verilator lint errors (let me know if you prefer that I remove these).

Fixes #140.

This patch fixes the baud rate calculation so that the behavior of simpleuart is in line with the description in picosoc/README.md: > The UART Clock Divider Register must be set to the system clock > frequency divided by the baud rate. Previously, the effective behavior of simpleuart was divisor = (clock frequency / baud rate) - 2 The fix is done basically by comparing `*_divcnt + 1 >= cfg_divider` instead of the old `*_divcnt > cfg_divider`. A special case is needed in the receive logic for the case where the divider is equal to 1, where at the next cycle we want to read the first bit (jumping straight to a `recv_state` of 2). This patch also makes some minor stylistic changes that fix Verilator lint errors.
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