How to fix the delay error in my Verilog code?

Question

I want to use a delay with # symbol, but the code gives error because of it. If I remove it, then the program works. Here is the code:

module b5( input wire switch, output wire led ); #100 assign led = switch; endmodule

Greg · Accepted Answer · 2014-11-12 18:23:57Z

The delay is in the wrong location. it should be assign #100 led = switch;

FYI: # delays only work in simulations. If you plan on synthesizing (such as running on FPGA), then you cannot use # delay. Use a clocked pipe-line instead.

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