Why this output get out with one delay?

Question

I made 4_to_1 MUX with 2_to_1 MUX. I used always syntax. The output is delayed one time unit, but I don't know why. When I change the always condition of 4_to_1 MUX's module sel to *, it works well. Why is this working?

module MUX_2_to_1 ( a0,a1,sel,out); input [3:0]a0; input [3:0]a1; input sel; output reg [3:0]out; always @(sel) begin if (sel == 0) out <= a0; else if (sel == 1) out <= a1; end endmodule

*

 module MUX_4_to_1( x0,x1,x2,x3,sel,out); input [3:0]x0; input [3:0]x1; input [3:0]x2; input [3:0]x3; input [1:0]sel; output reg [3:0]out; wire [3:0]w0; wire [3:0]w1; MUX_2_to_1 m0 (x0,x1,sel[0],w0); MUX_2_to_1 m1 (x2,x3,sel[0],w1); always @(sel) begin if(sel[1] == 0) out <= w0; else if (sel[1] == 1) out <= w1; end endmodule

*

`timescale 100ps/1ps module Testbench_Mux; reg [3:0]x0; reg [3:0]x1; reg [3:0]x2; reg [3:0]x3; reg [1:0]sel; wire [3:0]out; MUX_4_to_1 m0 (x0,x1,x2,x3,sel,out); initial begin x0 = 4'b0001; x1 = 4'b0010; x2 = 4'b0100; x3 = 4'b1000; #0 sel = 2'b00; #5 sel = 2'b01; #5 sel = 2'b10; #5 sel = 2'b11; #5 $stop; end endmodule

toolic · Accepted Answer · 2020-04-19 13:19:34Z

You are not using recommended Verilog coding practices for combinational logic. One problem is that you used an incomplete sensitivity list:

always @(sel)

Since there are 2 other signals, w0 and w1, which are read in the always block, they must also be in the sensitivity list. The verbose way to do this is:

always @(sel or w0 or w1)

The preferred way to do this is to use the compact * syntax:

always @(*)

This assures that the always block will be triggered when any change occurs to any signal read in the block.

Another issue is that you should always use blocking assignments for combinational logic. There is ample documentation out there as to the reason. Change <= to =:

always @(*) begin if(sel[1] == 0) out = w0; else if (sel[1] == 1) out = w1; end

If you don't follow these recommendations, you get undesired simulation results.

You should change your MUX_2_to_1 module as well.

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