Can someone give me a hint as to why this interface with modports and clocking blocks might not work?
interface axis (input logic aclk ); logic [15:0] tdata_s; logic tvalid_s; logic tready_s; logic [15:0] tdata_m; logic tvalid_m; logic tready_m; // clocking block for AXI Stream master clocking cb_axis_mst @(posedge aclk); default input #1step output #3ns; output tdata_m; output tvalid_m; input tready_m; endclocking // clocking block for AXI Stream slave clocking cb_axis_slv @(posedge aclk); default input #1step output #1ns; input tdata_s; input tvalid_s; output tready_s; endclocking // AXI stream master modport for testbench only modport tb_axis_mst_mp(clocking cb_axis_mst); // AXI stream slave modport for testbench only modport tb_axis_slv_mp(clocking cb_axis_slv); endinterface QuestaSIM 10.5c gives me a series of errors like this:
** Error: (vsim-3773) ../../../../rtl/test_driver.sv(37): Interface item 'tvalid_m' is not in modport 'tb_axis_mst_mp'.
The problem goes away if I add the ports to the modport, but my understanding was that it was sufficient to just use the clocking block.
Full code is here: https://www.edaplayground.com/x/5FzC
