I am generating a PLL simulation model. I can find the input ref clock period by using $time and divide the period with pll divider to generate pll output clock. as shown below, but simulator doesn't show anything on waveform , no syntax error though. What is wrong with this approach ?
time prev_t, periodd; reg clk = 0; always @(posedge CLK_PLL_IN) begin periodd = $time - prev_t; prev_t = $time; end always #(periodd/pll_div) clk = ~clk; The initial value of periodd is 0, so you get into a zero delay loop if the second always block begins before the first. I also suggest using realtime and $realtime instead of time and $time in case the factional part of periodd/pll_div is smaller than the timescale.
realtime prev_t, periodd=0; reg clk = 0; always @(posedge CLK_PLL_IN) begin periodd = $time - prev_t; prev_t = $time; end initial wait(periodd >0) forever #(periodd/pll_div) clk = ~clk; 