Issue with simulation timing

To answer your second question:

`timescale is a compiler directive. Using compiler directives can cause compile order dependencies, that is different behaviour or problems that are caused by the actual order you compile your files in. Suppose you have three files:

fileA.v `timescale 1ns/1ps fileB.v `timescale 10ns/10ps fileC.v // no timescale directive 

If you compile in this order

fileA.v fileB.v fileC.v 

then the precision will be 1ps - the smallest the compile found - the timeunit for each file will be:

fileA.v 1ns because of the `timescale directive fileB.v 10ns because of the `timescale directive fileC.v 10ns because the `timescale directive from fileB.v continues to have an effect 

If you compile in this order

fileA.v fileC.v fileB.v 

then the precision will be 1ps - the smallest the compile found - the timeunit for each file will be:

fileA.v 1ns because of the `timescale directive fileB.v 10ns because of the `timescale directive fileC.v 1ns because the `timescale directive from fileA.v continues to have an effect 

If you compile in this order

fileC.v fileA.v fileB.v 

then you will get an error, because it is illegal to have a file with no timescale directive appearing before any file with a timescale directive. (Though it is OK if no file has a `timescale directive).

timeunit and timeprecision are newer, System-Verilog ways of achieving the same thing. As they are not compiler directives, they do not suffer from the related problems. They only apply to the scope ($unit/package/module/program/interface) that they are used in (and must come first in that scope).

If you use timeunit and timeprecision as well as a timescale directive, then timeunit and timeprecision take priority.