SystemVerilog module that stores date and time

Question

VHDL does not have any method to get system date and time until VHDL 2019. This means that if I need to store the FPGA design synthesis time when an FPGA design is compiled, or when simulation is run, it is not possible. There are some workarounds that use something outside VHDL to generate date-time value and then pass this value into the synthesis code or the testbench.

Now this question is about SystemVerilog. Does SystemVerilog have a method whereby one can generate a logic vector storing the date-time value? For synthesis code the value shall be for when the function was invoked which is when synthesis was initialized. For simulation it shall be for when the simulation was executed.

dave_59 · Accepted Answer · 2024-07-15 17:23:10Z

Although SystemVerilog has no standard way, this can easily be accomplished with text macros at compile time, DPI calls into C, or using the $system function.

For example

vlog "+define+LOCAL_TIME_Sec=`date +%s`" myfile.sv

You can also find user contributed packages like svLib.

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