Linked Questions

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example: logic [15:0] down_vect; logic [0:15] up_vect; down_vect[lsb_base_expr +: width_expr] up_vect [...

Is it possible to create a parameter array in Verilog? For example, anything like the following: parameter[TOTAL-1 : 0] PARAM_ARRAY = {1, 0, 0, 2} If it is not possible, what could be the alternative ...

I am trying to create a for loop that assigns different values to a logic array given the iteration of the loop. So, for instance, let's say I am trying to instantiate two different bricks, both with ...

I have three wires created like this: wire [11:0] magnitude; wire [3:0] bitsEnd; wire [3:0] leadingBits; All of them are assigned some expression using combinational logic. The following code works ...

i'm implementing an instance of single cycle MIPS processor. i want to implement store half-word and store byte I've added a new input signal to my "Data memory" to control what to store like the ...

I'm new to Verilog and I would really appreciate it if someone could help me out with this error: output reg [0:image_width][image_height:0] result .... integer i, j, imageX, imageY, x, y, ...

I have a problem with the code below. The code is synthesized in ISE 14.2. input [1:8176] m_d_in; reg [1:511] m_d [1:16]; integer i; always @ (*) begin for (i=0; i<16; i=i+1) begin ...

I have a code like this: generate genvar i, j, k; for (i = 0, j = 8, k = 0; i < 4; i = i + 1, j = j + 8, k = k + 8) Register Register_inst (.d(w_data), .en(decoder_out[i]), .clk(clk), .q(...

I'm tring to write universal fifo buffer. To make it universal i used code like this. genvar i; generate for(i=0;i<BusWidthIn;i=i+1) begin: i_buffin always @ (negedge clkin) begin if (!full) ...

I have written a code for a 52 bit multiplier that I need to give out in standard form (IEEE 754 Floating point standard for 64 bit numbers). So afterwards I am checking, how many bits has it exceeded ...

For example, here: a = b[16:0] + c[0+:WIDTH]; What does the + sign do? Let's say b was 16'h1234 and c was 16'ABCD.

I get an error saying 'Index is not supported in signal'. From what I can see the error is on the left hand side of the non-blocking assignment. Why does the code below give an error and is there a ...

module myfunction(); function [31:0] myfunction; input [31:0] a; localparam bytes = 4; begin for(i=0; i<4;i= i+1) begin ...

I have a case structure in Verilog with approximately 95 cases. case(address) 5'd0: header_buffer[7:0] <= writedata; 5'd1: header_buffer[15:8] <= writedata; ...

I have an input logic sequence and I would like to convert it to a parameter in order to add it elsewhere in my program. For example, module myModule(input logic[7:0] SW, output logic[7:0] LEDR); ...