I am encountering suspicious behavior with std::atomic_ref::is_lock_free() in Microsoft Visual Studio's C++ compiler (MSVC version 14.38.33130). The method returns true for a very large structure (...

Here is a possibly incorrect program for communicating between a function and a signal handler that might interrupt it. Assume that HandleSignal has been arranged to run as a signal handler. The ...

As the title states, I have a question about the visibility of memory operation guarantees with happens before order. I've read the cppref memory order and a previous C++ iso draft, but I still cannot ...

Before I get to my main question, I'm assuming that std::mutex::unlock() stops touching this as soon as it puts the mutex in a state where another thread might lock it - even though the call to unlock(...

Consider this outline of a simple multi-threaded application. It has one writer thread, and ten reader threads. #include <atomic> #include <thread> const int Num_readers{...

I'm playing around with lockless C++ programming, and I came up with a method for safely(?) transferring ownership of a non-thread-safe data structure (std::unordered_map<int, float> in my ...

In the following program, I want to print the output as 0102030405... so on The 0 should be printed from one thread, odd values should be printed from second thread and even values from third thread....

I was checking the size of std::atomic compared to T on different platforms (Windows/MSVC, Linux/GCC, Android/Clang). For intrinsic types (like int, int64_t, etc.), the size of std::atomic matches the ...

An acquire-like load... will keep everything (both stores and loads) BELOW the load/fence. But this doesn't mean that everything ABOVE/before the acquire-load will not move below... This means that ...

I’ve spent several hours studying memory orderings, but I still have some contradictions in my head. One of them concerns the Acquire/Release memory orders. Currently, my understanding is: No ...

I'm working on a cross-platform data structure and trying to define a compact union-based layout that allows atomic access to a 64-bit word, while also optionally accessing the lower 32-bit fields. I ...

Background I'm building a cross-platform atomic abstraction layer to support 64-bit and 128-bit atomic operations for the following types: int64_t, uint64_t __int128 (on Clang platforms) A custom ...

below is a copy screen from https://www.youtube.com/watch?v=5uIsadq-nyk, at 1:12:23, the line std::size_t seq2=seq.load(std::memory_order_relaxed) baffles me. I am not very familiar with the atomics, ...

The following code is very easy illustrating the release-consume ordering: std::atomic<int> a{ 0 }; std::atomic<bool> b{ false }; void t1() { a.store(1, std::...

#include <atomic> #include <thread> #include <cassert> #include <chrono> std::atomic<int> x {}, y {}; void write_x_and_y() { x.store(1, std::memory_order_seq_cst); ...