Programmable array logic

Programmable Array Logic Presentation By: Fareed Yousuf Jawwad Khatri Muhammad Afnan SMI University

 PLDs  Programmable Logic Devices (PLD)  General purpose chip for implementing circuits  Can be customized using programmable switches  Main types of PLDs  PLA  PAL  ROM  CPLD  FPGA  Custom chips: standard cells, sea of gates

 PLD as a Black Box Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions)

 Programmable Logic Array (PLA)  Use to implement circuits in SOP form  The connections in the AND plane are programmable  The connections in the OR plane are programmable f1 AND plane OR plane Input buffers inverters and P1 Pk fm x1 x2 xn x1 x1 xn xn

 Programmable Array Logic (PAL)  Also used to implement circuits in SOP form  The connections in the AND plane are programmable  The connections in the OR plane are NOT programmable f1 AND plane OR plane Input buffers inverters and P1 Pk fm x1 x2 xn x1 x1 xn xn fixed connections

 Limitations of PLAs  PLAs come in various sizes  Typical size is 16 inputs, 32 product terms, 8 outputs  Each AND gate has large fan-in  this limits the number of inputs that can be provided in a PLA  16 inputs  316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA  32 AND terms permitted  large fan-in for OR gates as well  This makes PLAs slower and slightly more expensive than some alternatives to be discussed shortly  8 outputs  could have shared minterms, but not required

 Example Schematic of a PAL f1 P1 P2 f2 x1 x2 x3 AND plane P3 P4 f1 = x1x2x3'+x1'x2x3 f2 = x1'x2'+x1x2x3

 Comparing PALs and PLAs  PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane  less flexibility than PLAs  PALs are simpler to manufacture, cheaper, and faster (better performance)  PALs also often have extra circuitry connected to the output of each OR gate  The OR gate plus this circuitry is called a macrocell

 Macrocell f1 back to AND plane D Q Clock Select Enable Flip-flop OR gate from PAL 0 1

 Macrocell Functions  Enable = 0 can be used to allow the output pin for f1 to be used as an additional input pin to the PAL  Enable = 1, Select = 0 is normal for typical PAL operation  Enable = Select = 1 allows the PAL to synchronize the output changes with a clock pulse  The feedback to the AND plane provides for multi- level design f 1 back to AND plane D Q Clock Select Enable 0 1

 Multi-Level Design with PALs  f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'  where g = BC + B'C' and C = h below D Q Clock Sel = 0 En = 0 0 1 D Q Clock Select 0 1 D Q Clock Sel = 0 En = 1 0 1 A B h g f

 ROM  A ROM (Read Only Memory) has a fixed AND plane and a programmable OR plane  Size of AND plane is 2n where n = number of input pins  Has an AND gate for every possible minterm so that all input combinations access a different AND gate  OR plane dictates function mapped by the ROM

 Programming SPLDs  PLAs, PALs, and ROMs are also called SPLDs – Simple Programmable Logic Devices  SPLDs must be programmed so that the switches are in the correct places  CAD tools are usually used to do this  A fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit  There are two basic types of programming techniques  Removable sockets on a PCB  In system programming (ISP) on a PCB  This approach is not very common for PLAs and PALs but it is quite common for more complex PLDs

 An SPLD Programming Unit  The SPLD is removed from the PCB, placed into the unit and programmed there

 Removable SPLD Socket Package  PLCC (plastic-leaded chip carrier) Printed circuit board PLCC socket soldered to the PCB

 In System Programming (ISP)  Used when the SPLD cannot be removed from the PCB  A special cable and PCB connection are required to program the SPLD from an attached computer  Very common approach to programming more complex PLDs like CPLDs, FPGAs, etc.

 CPLD  Complex Programmable Logic Devices (CPLD)  SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms  Combined number of inputs + outputs < 32 or so  CPLDs contain multiple circuit blocks on a single chip  Each block is like a PAL: PAL-like block  Connections are provided between PAL-like blocks via an interconnection network that is programmable  Each block is connected to an I/O block as well

 Structure of a CPLD PAL-like block I/Oblock PAL-like block I/Oblock PAL-like block I/Oblock PAL-like block I/Oblock Interconnection wires

 Internal Structure of a PAL-like Block  Includes macrocells  Usually about 16 each  Fixed OR planes  OR gates have fan-in between 5-20  XOR gates provide negation ability  XOR has a control input D Q D Q D Q PAL-like block PAL-like block

 Programming a CPLD  CPLDs have many pins – large ones have > 200  Removal of CPLD from a PCB is difficult without breaking the pins  Use ISP (in system programming) to program the CPLD  JTAG (Joint Test Action Group) port used to connect the CPLD to a computer

 FPGA  SPLDs and CPLDs are relatively small and useful for simple logic devices  Up to about 20000 gates  Field Programmable Gate Arrays (FPGA) can handle larger circuits  No AND/OR planes  Provide logic blocks, I/O blocks, and interconnection wires and switches  Logic blocks provide functionality  Interconnection switches allow logic blocks to be connected to each other and to the I/O pins

 Structure of an FPGA I/O block I/O block I/Oblock I/Oblock logic block interconnection switch

Programmable array logic

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