System Verilog Introduction with basics1

System Verilog INTRODUCTION, DATA TYPES

⚫ System Verilog is a hardware description and Verification language (HDVL). ⚫ It was developed by Accellera Systems Initiative and the IEEE Standards Association to address the growing complexity of modern digital systems. ⚫ System Verilog (IEEE Standard 1800-2005) is an extensive set of enhancements to IEEE 1364 Verilog- 2001 standards. ⚫ It inherits features from Verilog, VHDL, C and C++. ⚫ One of the key advantages of using SV is its ability to streamline the design and verification process. ⚫ Another significant advantage of System Verilog is its support for advanced verification techniques, such as the Universal Verification Methodology (UVM). What is SV?

Features of SV OOPS Constrained Randomizatio n Functiona l Coverage Synchronizatio n Improved Data Types Assertion s System Verilog

⚫System Verilog offers following Data Types: o 4-State Type o 2-State Type o Real o Arrays o User Define Data Type o Structures o Unions o Strings o Enumerated Type o Class

⚫Allowed values are 0, 1, X and Z. ⚫Following 4-State types are included from Verilog: o wire //Size: 1-bit Value: Z o reg //Size: 1-bit Value: X o integer // Size: 32-bit Value: X o time // Size: 64-bit Value: X ⚫User can define size for wire and reg. ⚫integer is signed, all others are unsigned. 4-State Type

⚫Addition to System Verilog o logic //Size: 1- bit ⚫User can define size for logic. Value: X ⚫Logic is improved reg data type. ⚫Logic can be driven by continuous as well as procedural assignments. ⚫Logic has a limitation that it cannot be driven by multiple drivers in such case use wire. 4-State Type

Logic endmodul Example1: module and_gate ( input logic a, b, output logic c); //driving logic using continuous assign c= a & b; assignment endmodule Example2: module flip_flop ( input logic din, clk, output logic dout); always @ (posedge clk) dout<=din; //driving logic using procedural assignment

Logic driver . Example3: module example3 ( input logic a, b, output logic c); assign c= a & b; //driving logic using continuous assignment always @ * c= a | b; assignmen t //driving logic using procedural eTnhdismcoodduelewill give compilation error because of multiple

Logic Compilation error, use wire to achieve this functionality. Example4: module example4 ( input logic a, b, ctrl, output logic c); assign c= ctrl?a:1’bZ; //driving logic using continuous assignment assign c= !ctrl?b:1’bZ; //driving logic using continuous assignmen t endmodul e

⚫Allowed values are 0 and 1. ⚫System Verilog offers following 2-State Data Types : ⚫ All are signed except bit which is unsigned. o shortint //Size: 16-bit Value: 0 o int //Size: 32-bit Value: 0 o longint //Size: 64-bit Value: 0 o byte //Size: 8-bit Value: 0 o bit //Size: 1-bit Value: 0 ⚫User can define size for bit. 2-State Type

Example1 c=‘0; end endmodul e // locations with given number module example1; int a; int unsigned b; bit signed [7:0] c; initia l begi n a=-32’d127; b=‘1; //unsigned integer //same as byte //SV offers un-sized literal to fill all

Example2 module example2; int a; logic [31:0] b=‘Z; initia l begi n a=b; b=32 ’h12 3x_5 678; //b=32’hzzzz_zzzz // a=32’h0000_0000 if($unknown(b)) $display(“b is unknown”); $display(“b is known”); else end end mo dul

⚫Included from Verilog o real //Default Value : 0 ⚫real is same as double in C. ⚫Addition to System Verilog o shortreal //Default Value : 0 o realtime //Default Value : 0 ⚫shortreal is same as float in C. ⚫realtime and real can be used interchangeably. Real Type

⚫void data type represents non existing data. ⚫It can be used as return type of functions to indicate nothing is returned. Void Usage: display() ; Example : function void display; $display(“Hello”) ; endfunction

⚫Arrays are used to group elements of same type. ⚫Arrays can be categorized as following: o Fixed Array o Dynamic Array o Packed Array o Unpacked Array o Queues o Associative Array Arrays

⚫Array whose size is fixed during compilation time is called as Fixed Array. ⚫Size of fixed array cannot be modified during run time. element Fixed Array Examples int array1 [15]; elements //array of int containing 15 //Equivalent to int array1 [0:14] int array2 [0:14]; logic array3 [7:0]; //array of logic containing 8

⚫Unpacked Arrays can be declared by adding size after array name. ⚫Unpacked Arrays can be made of any data type. Example: ⚫System Verilog stores each element of an unpacked array in a longword (32-bit). Unpacked Array int array1 [16] [8]; bit array2 [3:0] [7:0]; bit [7:0] array3 [4]; //16 rows , 8 columns //4 rows , 8 columns //4 rows each containing 8 bits

Unpacked Array bit [7:0] array1 [4]; array1 [2] array1 [3] Unus ed 7 6 5 4 3 2 1 0 Unu sed 7 6 5 4 3 2 1 0 array1 [0] Memory array1 [1] Memory Unu sed 7 6 5 4 3 2 1 0 Memory Unu sed 7 6 5 4 3 2 1 0 Memory

Unpacked Array }; Initializing Array: int array1 [2] [4] = ‘{ ‘{ 1, 2, 3, 4 } , ‘{ 5, 6, 7, 8 } }; int array2 [2] [3] = ‘{ ‘{ 1, 3, 6 } , ‘{ 3 {2} }; // same as ‘{ 1, 3, 6 } , ‘{ 2, 2, 2 } int array3 [0:5] = ‘{1:5, 3:1, default: 0}; // same as ‘{0, 5, 0, 1, 0, 0} int array4 [0:2] [1:4] = ‘{3 { ‘{ 2 {1, 2} } } }; // same as ‘{ ‘{1, 2, 1, 2} , ‘{1, 2, 1, 2} , ‘{1, 2, 1, 2} } int array5 [2] [2] [2] = ‘{ ‘{ ‘{4, 5}, ‘{3, 1} }, ‘{ ‘{1, 7}, ‘{2, 5} }

Unpacked Array Accessing Array int array1 [2] [4]; int array2 [0:5]; byte array3 [0:2] [1:4]; int a, b; byte c; a= array1[1] [3]; b= array2[4]; c= array3[1] [2];

Basic Array Operation ⚫Arrays can be manipulated using for and foreach loop bit [7:0] array1[10], array2[10] ; initia l begi n for ( int i=0; i <$siz e(arr ay1); //$size returns size of //k is defined implicitly

Basic Array Operation Example: bit [7:0] array1[10] [20]; initia l begi n array 1=‘{1 0 { ‘{0: 2, 1 : 0 ,

⚫Packed Arrays can be declared by adding size before array name. ⚫One dimensional packed arrays are also referred as vectors. ⚫Packed array is a mechanism of subdividing a vector into subfields which can be accessed as array elements. ⚫Packed array represents contiguous set of bits. ⚫Packed array can be made of single bit data (logic, bit, reg), enumerated type or other packed arrays. Packed Array

Packed Array bit [3:0] [7:0] array1; 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 array1[3 ] bit [7:0] a, b; bit [15:0] c; bit d; bit [31:0] e; ] array1[1 array1[0] [4] array1[3:2 ] array 1 e=array1 ; a=array1[3]; b=array1[1]; c=array1[3:2]; d=array1[0] [4];

Packed Array 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Mixture of Packed and Unpacked Array bit [3:0] [7:0] b [4]; b[0] 7 6 5 4 3 2 1 0 7 6 5 [ 2 4] 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 b[1 ] b[2 ] b[3 ] b[0] [2] b[1 ] b[2] [2] b[3] [0] b[0] [1] [4:0]

Packed vs. Unpacked Array ⚫ Packed arrays are handy if user wants to access array with different combination. ⚫ If user want to wait for change in array(i.e. @), in that case packed array will be preferred over unpacked array. ⚫ Only fixed size arrays can be packed. Therefore it is not possible to pack following arrays: o Dynamic Arrays o Queues o Associative Arrays

Operation on Arrays int A [0:7] [15:0] , B [0:7] [15:0]; ⚫Following operation are possible for both packed and unpacked arrays. ⚫Both array A and B should be of same type and size. A=B; A[0:3]= B[0:3]; A[1+:4]= B[3+:4]; A[5]=B[5]; A==B A[2:4]! =B[2:4]; //Copy Operation //Slice and Copy //Comparison Operations

Operation on Arrays bit [3:0] [7:0] A; ⚫Following operation are only allowed in packed arrays: A=0; A=A + 3; A=A * 2; A=‘1; A=A & 32’d255; A[3:1]=16’b1101_1110_0000_1010;

⚫Dynamic arrays are unpacked arrays whose size can be set and changed during simulation time. ⚫new constructor is used to set or change size of Dynamic Array. ⚫size() method returns current size of array. ⚫delete() method is used to delete all elements of the array. Dynamic Array

Dynamic Array int dyn1 [ ]; int dyn2 [4] [ ]; //Defining Dynamic Array (empty subscript) initial begin dyn1=new[10]; foreach (dyn1[ i ]) dyn1[ i ]=$random; dyn1=new[20] (dyn1); //Allocate 10 elements // Initializing Array // Resizing array and // Copying older values // Resizing to 50 elements Old Values are lost // Delete all elements dyn1=new[50 ]; dyn1.delete; end

Dynamic Array int dyn1 [ ]= ‘{5, 6, 7, 8} ; //Alternative way to define size initial begin repeat (2) if (dyn1.size != 0) begin foreach(dyn1 [ i ] ) $display(“dyn1 [%0d]=%0d”, i, dyn[ i ] ); dyn1.delete; en d else

⚫System Verilog allows user to define new data types using typedef keyword. User Defined typedef byte unsigned uint8; typedef bit [15:0] word; //Defining uint8 //Defining word uint8 a, b; word c, d; a=8’d10; c=16’d25;

⚫System Verilog string type is used to store variable length strings. ⚫Each character of string is of type byte. ⚫There is no null character at the end of string. ⚫String uses dynamic memory allocation, so size of string is no longer a concern. Example : string s=“hello”; String

String Operators ⚫str1 == str2 checks whether strings are equal or not. ⚫str1 != str2 checks for inequality of strings. ⚫Comparison using lexicographical ordering of strings. o str1 < str2 o str1 <= str2 o str1 > str2 o str1 >= str2 ⚫{str1, str2, str3, .. , strn} concatenation of strings.

String Operators Example : string s1=“hello”, s2=“Hello”, s3=“xyz”; initial begin if(s1 != s2) $display(“strings are different”); if(s1 > s3) $display(“s1 is more than s3”); else $display(“s3 is more than s1”); $display({s1, s2, s3}); end

String Methods ⚫len() method returns length of a string. ⚫putc(position, character) method replaces character at given position by character passed as an argument. ⚫getc(position) method returns ASCII value of character at given position. ⚫toupper() method returns a string with all characters in uppercase.

String Methods ⚫tolower() method returns a string with all characters in lowercase. ⚫compare(string) compares given string with string passed as an argument. ⚫icompare(string) same as above but comparison is case insensitive. ⚫substr(i, j) returns a string formed between characters at position i and j.

String Methods ⚫atoi() method returns integer corresponding to ASCII decimal representation. ⚫The conversion scans all leading digits and underscore characters ( _ ) and stops as soon as it encounters any other character or the end of the string. ⚫itoa(i) stores the ASCII decimal representation of i in sEtrxinagm.ple : string s1=“12_3xyz”, s2; int a, b=127; a=s1.atoi(); //a=123 s2.itoa(b); // s2=“127”

String Methods //Display: 83 (‘S’) // Display: SYSTEMVERILOG // "SystemVerilog3.1b" // change b-> a // Display: stem s2=$psprintf("%s %0d", s1, 5); $display(s2); // Display: SystemVerilog3.1a 5 end Example : string s1, s2; initial begin s1 = "SystemVeri log"; $display(s1. getc(0)); $display(s1.toupper() ); s1 = {s1, "3.1b"}; s1.putc(s1.len()-1, "a"); $display(s1.substr(2, 5));

⚫An enumeration creates a strong variable type that is limited to a set of specified names. Example : enum { RED, GREEN, BLUE } color; typedef enum { FETCH, DECODE, EXECUTE } operation_e; ⚫enum are stored as int unless specified. typedef enum bit [2:0] { RED, GREEN, BLUE } color_e; ⚫First member in enum gets value 0, second value 1 and so on. ⚫User can give different values to member if required. Enumerated Type

Enumerated Type Example : enum { RED, GREEN, BLUE } color; //RED=0, GREEN=1, BLUE=2 enum { GOLD, SILVER=3, BRONZE} medals; //GOLD=0, SILVER=3, BRONZE=4 enum {A=1, B=3, C, D=4} alphabet; //Compilation error C and D have same value enum logic [1:0] {A=0; B=‘Z, C=1, D} exam; //A=00, B=ZZ, C=01, D=10 Default value of exam is X

⚫first() method returns first member of enumeration. ⚫last() method returns last member of enumeration. ⚫next(N) method returns the Nth next member (default is 1) starting from current position. ⚫previous(N) method returns Nth previous member (default is 1) starting from current position. Enumerated Type Methods

⚫Both next() and prev() wraps around to start and end of enumeration respectively. ⚫num() method returns number of elements in given enumeration. ⚫name() method returns the string representation of given enumeration value. Enumerated Type Methods

Enumerated Type Methods Example typedef enum { RED, BLUE, GREEN} color_e; color_e mycolor; mycolor = mycolor.first; do begin $display("Color = %0d %0s", mycolor, mycolor.name); mycolor = mycolor.next; end while (mycolor != mycolor.first); // Done at wrap- around

const ⚫const keyword is used to define constants in System Verilog. ⚫localparam constants are set during elaboration time. ⚫const constants are set during simulation time. Example: const byte colon= “:”; const real pi=3.14;

Events • Events are static objects useful for synchronization between the process. • Events operations are of two staged processes in which one process will trigger the event, and the other processes will wait for an event to be triggered. • Events are triggered using -> operator or ->> operator. • wait for an event to be triggered using @ operator or wait() construct • System Verilog events act as handles to synchronization queues. thus, they can be passed as arguments to tasks, and they can be assigned to one another or compared. • Syntax: a) ->event_name; b) @(event_name.triggered);

Casting ⚫Casting is used convert data from one type to other. ⚫There are two ways to perform casting : o Static Casting: destination = return_type’ (source). This type of casting always succeeds at run time and does not give any error. o Dynamic Casting: using $cast system task or function. Example : int a; initial a=int’(3.0 * 2.0);

Casting ⚫System Verilog provides the $cast system task to assign values to variables that might not ordinarily be valid because of differing data type. ⚫ $cast can be called as either a task or a function. $cast used as a function if ($cast(destination, source)) source // should be singular $cast used as a task $cast(destination, source); //destination and

Casting int a; real b=3.0; if($cast(a, b)) //Returns 1 if casting succeeds else 0 $display(“casting success”); $cast(a, b); //If casting fails run time error occurs In both cases if casting fails then destination value remains unchanged.

Casting Example : int a=- 10; initia l begi n $dis play( a>>> 1); $dis // -5 // positive value // changing to constant

Casting typedef enum { red, green, blue, yellow, white, black } Colors; Colors col; int a, b; initial begin col=green; //col=3; a= blue * 2; b= col + green; end Runtime error

Casting en d typedef enum { red, green, blue, yellow, white, black } Colors; Colors col; initial begin $cast( col, 2 + 3 ); // col=black if ( ! $cast( col, 2 + 8 ) ) $display( "Error in cast" ); //10: invalid cast col = Colors’(2 + 1); col = Colors’(4 + 3); //col=yellow //value is empty

Loops ⚫Included from Verilog • for • forever • repeat • while ⚫Additions to System Verilog o foreach o do while

Loops inital begin int a [8] [5]; foreach ( a [i, j] ) a[i] [j]=$rando m; end inital begin int i=10; do begin i -=1; //statements end while (i >5) end Statements executed first an then execution depends upon condition Used to access all elements in an array

Break and Continue inital begin int i; repeat(10) begin if(i==7) break; i+=1; en d en inital begin int i; repeat(10) begin if(i==7) continue; i+=1; en d en

If-else Expression Futurewiz www.futurewiz.co.i ⚫It is possible to select property expression based on some condition using if-else expression. property test; @(posedge clk) (req1 || req2) -> if(req1) ##1 ack1; else ##1 ack2; endpropert y

System Verilog Introduction with basics1

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