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fixed grammar
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edit approved Oct 23 at 20:50
SnappyRiffs
edit approved Oct 23 at 20:50
SnappyRiffs
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Can I do multi bit cdc useCDC using synchronizers without handshake or FIFO?

I know that asynchronous fifoFIFO and handshake can do cdcCDC, but the fifoFIFO consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?

always @(posedge dst_clk) dst0 <= src; always @(posedge dst_clk) dst1 <= dst0; always @(posedge dst_clk) dst2 <= dst1; always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;

I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?

Can I do multi bit cdc use synchronizers without handshake or FIFO

I know that asynchronous fifo and handshake can do cdc, but the fifo consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?

always @(posedge dst_clk) dst0 <= src; always @(posedge dst_clk) dst1 <= dst0; always @(posedge dst_clk) dst2 <= dst1; always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;

I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?

Can I do multi bit CDC using synchronizers without handshake or FIFO?

I know that asynchronous FIFO and handshake can do CDC, but the FIFO consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?

always @(posedge dst_clk) dst0 <= src; always @(posedge dst_clk) dst1 <= dst0; always @(posedge dst_clk) dst2 <= dst1; always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;

I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?

fix formatting
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Dave Tweed
Dave Tweed
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I know that asynchronous fifo and handshake can do cdc, but the fifo consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?
always @(posedge dst_clk) dst0 <= src;
always @(posedge dst_clk) dst1 <= dst0;
always @(posedge dst_clk) dst2 <= dst1;
always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;
I

always @(posedge dst_clk) dst0 <= src; always @(posedge dst_clk) dst1 <= dst0; always @(posedge dst_clk) dst2 <= dst1; always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;

I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?

I know that asynchronous fifo and handshake can do cdc, but the fifo consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?
always @(posedge dst_clk) dst0 <= src;
always @(posedge dst_clk) dst1 <= dst0;
always @(posedge dst_clk) dst2 <= dst1;
always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;
I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?

I know that asynchronous fifo and handshake can do cdc, but the fifo consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?

always @(posedge dst_clk) dst0 <= src; always @(posedge dst_clk) dst1 <= dst0; always @(posedge dst_clk) dst2 <= dst1; always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;

I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?

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zaryleik
zaryleik
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Can I do multi bit cdc use synchronizers without handshake or FIFO

I know that asynchronous fifo and handshake can do cdc, but the fifo consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?
always @(posedge dst_clk) dst0 <= src;
always @(posedge dst_clk) dst1 <= dst0;
always @(posedge dst_clk) dst2 <= dst1;
always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;
I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?