I know that asynchronous fifo and handshake can do cdc, but the fifo consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I want to synchronize it to "dst_clk" as "dst", can I simply sample it like this?
always @(posedge dst_clk) dst0 <= src;
always @(posedge dst_clk) dst1 <= dst0;
always @(posedge dst_clk) dst2 <= dst1;
always @(posedge dst_clk) if (dst1 == dst2) dst <= dst2;
I think dst0 and dst1 can eliminate metastability, and dst2 validate the new value is correct, is my idea correct? And if I need to set_max_delay between src and dst0?