Questions tagged [metastability]
Questions about the behaviour of FlipFlops when the normal input setup or hold requrements are not respected, usually when launch and capture clocks are not synchronous.
47 questions
1 vote
1 answer
104 views
Can I do multi bit CDC using synchronizers without handshake or FIFO?
I know that asynchronous FIFO and handshake can do CDC, but the FIFO consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I ...
- 13
7 votes
5 answers
1k views
FPGA metastability when going from a slow clock to faster clock?
I am new to FPGA, and I keep reading articles about how it is critical to double flop any sampled signal when going from a slow clock domain to a fast clock domain... https://nandland.com/lesson-14-...
- 10.4k
-2 votes
1 answer
144 views
Metastability between FPGA and C server via UART [closed]
I am planning to build a communication channel between my laptop (running a simple C server) and my FPGA using UART. Do I need to worry about metastability? I suppose to be more specific, I am ...
- 641
0 votes
1 answer
122 views
How does a Lattice MachXO3LF FPGA handle undefined IO states?
In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this? How does the FPGA handle if the undefined state was reached ...
- 37
1 vote
1 answer
238 views
Is there metastability concern in the design of "slicer" part of serdes receiver circuit?
It seems that metastability is an important aspect of concerns when designing sequential circuits. This related to the fact that the signal must wade through the "forbidden zone" when it ...
- 523
1 vote
5 answers
265 views
Why would an intermediate voltage level cause a metastability in a SR-latch
Transistors and logic gates are actually analog in nature they aren't digital they don't turn on or off at certain voltages. Image source: All About Circuits - Voltage Tolerance of CMOS Gate Inputs ...
- 301
0 votes
2 answers
232 views
Shared FIFO control module between UART, PS/2 protocol, UART is ok, PS/2 has issue locking on to packets during read
I have brought over a design from a previously provided source in my FPGA. This is the FIFO controller for my system that gets instantiated in both UART sub system, as well as PS/2 sub system. The ...
- 181
4 votes
2 answers
1k views
Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily". So, my question is: Why do almost all of ...
- 309