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Questions tagged [synchronization]

Synchronization is the coordination of events to operate a system in unison. In digital systems this is usually accomplished by using a clock signal. (From: Wikipedia)

2 votes
7 answers
772 views

Hello, I want to design a blinking LED module that can run stand-alone, but also synchronize with other identical modules over a single shared SYNC wire. The behavior I’m trying to achieve is: Each ...
mete5050's user avatar
2 votes
1 answer
105 views

As a hobby project and a way to learn, I'm trying to make a 1x2 RGBHV distribution amplifier. I've got the amplification for the RGB part mostly figured out but I'm clueless on how to deal with the H/...
JayD's user avatar
  • 31
1 vote
1 answer
104 views

I know that asynchronous FIFO and handshake can do CDC, but the FIFO consume more resource, and handshake is a little complicated. If I have a multi bit signal "src", and it vary slowly, I ...
zaryleik's user avatar
-1 votes
1 answer
125 views

I have been studying the clock muxed from this source: https://vlsitutorials.com/glitch-free-clock-mux/ In this and many other websites, the clock mux is a flip-flop-based circuit. From what I ...
Erinç Utku Öztürk's user avatar
2 votes
0 answers
65 views

Today I started working with an experimental system that uses two lasers, various optics, and a master clock to control timing. The lasers, external triggers, and other devices are all connected via ...
dareen's user avatar
  • 531
4 votes
1 answer
102 views

I'm not sure if this is the right place to post this, but I'm dealing with PPS (pulse per second) signals at the end of the day. I am working with multiple GNSS receivers (from different manufacturers,...
louisbzk's user avatar
2 votes
1 answer
223 views

Suppose I have 3 separate square-wave digital 5V clocks, named A, B and C. All 3 clocks are ...
Runsva's user avatar
  • 587
0 votes
0 answers
58 views

Im currently trying to acheive some rough phase coherence between two rtl-sdr dongles, the dongles share a single 28.8 MHz clock signal (from V4 to V3). However, there seems to be some phase drift ...
Allfadern's user avatar
1 vote
1 answer
82 views

So here's the question And the answer given in the solutions The textbook (digital design and computer architecture 2e) says that MTBF (Mean Time Between Failures) for synchronizers is Which makes ...
PlusOneDelta's user avatar
1 vote
0 answers
41 views

I’m seeking help with synchronizing two APSIN2010 waveform generators to produce synchronized sine wave pulses. Specifically, I need to align both the frequency and timing between the two devices. I ...
iwantaskquestion's user avatar
2 votes
0 answers
66 views

Is there an order of magnitude guesstimate on how accurate of a time sync a PTP capable device can achieve given its packet timestamping method? I have an FPGA COTS board with a standard/non-1588-...
Sittin Hawk's user avatar
0 votes
1 answer
81 views

suppose a signal is coming from a slower to a faster clock domain, and 2 levels of synchronizing FFs have been used, then the tool shows failing path from the launch node to the first synchronizing ...
lousycoder's user avatar
1 vote
2 answers
98 views

I'm working on a design where I have a need to generate about 10A at 5V across a long bar-shaped board. This is generated from an incoming 12V DC rail. For a number of reasons (physical constraints, ...
Polynomial's user avatar
  • 11.5k
0 votes
2 answers
131 views

When I synchronize two computers' system clocks up to 0.5 ms precision using NTP protocol implementation, it reports several tens of milliseconds skew in less than 10 minutes, and up to 3000 ms skew ...
ivan866's user avatar
  • 101
5 votes
4 answers
883 views

I would like to build a SIMPLE circuit that generates PAL sync signals with no MCUs, because they don't make any ICs of these kind anymore. I have already tried a solution, but I think it is ...
Vargánya Művek's user avatar

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