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I found that I could not get a T Flip-Flop without a reset to simulate in SystemVerilog, but I could get a JK Flip-Flop without a reset to simulate. This is because I can set a JK Flip-Flop to a known state using J = 0, K = 1 or K = 1, J = 0.

The design code:

module t_ff(input logic t, clk, output logic q, q_bar); parameter HOLD = 1'b0, TOGGLE = 1'b1; always_ff @(posedge clk) case (t) HOLD: q <= q; TOGGLE: q <= ~q; default: q <= 1'bz; endcase assign q_bar = ~q; endmodule

I tried using bit in the testbench, but that did not work either (just as I expected). I understand that a reset is important for a Flip-Flop in IC Design, but can't we build a Flip-Flop without a reset? I think the T Flip-Flop can be used without a reset in applications when the input for the flip-flop comes from another digital circuit.

How is this problem handled in Gate-level simulations?

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  • \$\begingroup\$ Use an initial statement to put q in a known state at the beginning of the simulation. This will have no effect on synthesis. \$\endgroup\$ Commented Feb 28, 2021 at 11:24
  • \$\begingroup\$ That would depend on exactly what syntheses tool you're using to get from RTL to a gate-level design. \$\endgroup\$ Commented Feb 28, 2021 at 12:43
  • \$\begingroup\$ @DaveTweed I tried what you said using both Cadence and Siemens simulators, but it did not work as I got an error and the simulation halted. Can you give me a testbench that works for you? \$\endgroup\$ Commented Feb 28, 2021 at 12:54
  • \$\begingroup\$ The simulator is modeling how the T flip-flop would really work, unfortunately. As @DaveTweed suggested, look for some non-standard feature in your simulation tool, or use a different flip-flop. \$\endgroup\$ Commented Feb 28, 2021 at 13:11

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Reset to default
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As for "how is this handled in gate level simulation", I've done vlsi design in industry for 15 years and I've never seen a T flip flop since college. A TFF without reset is nonsensical since you can never know what the value is. You could conceivably make a circuit that asserts T if the output is 1 through some FSM that activates once, to put the TFF in a known state. I would call that "reset".

But if you insist, some simulators have a mode to randomly initialize every flip flop in the design. This can be helpful for gate level sims.

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    \$\begingroup\$ I think you will find that there are many questions on this site that are only of academic interest. Sometimes barely even that. Often we get obscure homework questions that must be solved in some specific manner. \$\endgroup\$ Commented Mar 1, 2021 at 2:32
  • \$\begingroup\$ Thanks for this great answer! I am still a student and have not got a chance to work in the VLSI Design industry yet. So it is new information to me that a T Flip-Flop without reset is useless, although I had suspected it would be useless in my answer here: electronics.stackexchange.com/a/540545/238188 \$\endgroup\$ Commented Mar 1, 2021 at 5:37

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