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In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper clock-domain crossing?

At the moment, I'm assuming the calculation for the number of stages should go something like this

200/30 = 6.67

As such, I'd need 7 flip-flop stages to be able to meet the clock-domain crossing requirement. Is this a correct assumption?

The system has multiple control signals and a couple of data-buses going back and forth. The widest bus is 32-bits while the smallest bus is 24-bits.

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  • \$\begingroup\$ Sounds right to enable flow control plus margin for prop.delay and latency. But could be more. \$\endgroup\$ Commented Nov 10, 2021 at 16:47
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    \$\begingroup\$ Frequency of clocks and no. of flops in synchronizer chain has no relationship like you calculated. 2 stage FF synchronizer is enough for low/medium speed designs.....but you should provide us more information on what is passed and in what direction. Is it multi bit/single bit signal etc.. \$\endgroup\$ Commented Nov 10, 2021 at 17:06
  • \$\begingroup\$ @mitu-raj, thanks for the reply! Just added some more details to my inquire. \$\endgroup\$ Commented Nov 10, 2021 at 17:30
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    \$\begingroup\$ ... to meet the clock-domain crossing requirement What clock-domain crossing requirement? Go 200->30, and you cannot of course capture all the data. Go 30->200, and only one flop is needed for the data, with 2 or 3 for control signals to meet metastability requirements. \$\endgroup\$ Commented Nov 10, 2021 at 18:41
  • \$\begingroup\$ I think you only need 3 FF's, properly connected and driven, to guarantee metastable-free signal crossing from one cock domain to another, irrespective of what the two domain clock frequencies are. \$\endgroup\$ Commented Nov 11, 2021 at 0:30

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The number of flip flops needed depends on three things:

  • target MTBF requirement
  • clock rate
  • ‘crunchiness’ of the flip flops

The latter point, ‘crunchiness’, is also called metastable hardness, and it means the flip-flop’s own intrinsic MTBF. This is related to the speed of of the flop: faster ones with shorter setup/hold times and high feedback gain are crunchier than slow ones.

More here: http://www.interfacebus.com/Design_MetaStable.html

Here too: https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf

In most cases, with today’s logic and clock speeds in the 10s to 100s of MHz, two flip flops will yield adequate MTBF.

Related: Why do cascading D-Flip Flops prevent metastability?

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    \$\begingroup\$ Super useful links in this post thanks. Metastable hardness is a cool concept. \$\endgroup\$ Commented Nov 18, 2021 at 11:56

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