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In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this?

How does the FPGA handle if the undefined state was reached from a previous logic high, or a previous logic low?

I am using a LCMXO3LF-4300E-5MG121I FPGA, LVCMOS1.2 with a 3.3 VCCIO of 3.3V. In Lattice Diamond, these setting synthesized and mapped without error, Hysteresis only option is NA.

Here are links to the FPGA Family's webpage, data sheet, as well as a sysIO user guide.

https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3

https://www.latticesemi.com/view_document?document_id=50121

https://www.latticesemi.com/view_document?document_id=50125

Thank you!

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    \$\begingroup\$ That depends how you configure the input. Which input configuration you mean? For example, are bus keepers enabled to provide hysteresis? \$\endgroup\$ Commented May 31, 2024 at 22:02
  • \$\begingroup\$ What is the source of the input, and is the change in voltage monotonic? The actual behaviour of the FPGA might depend upon the slew rate of the input signal. \$\endgroup\$ Commented Jun 1, 2024 at 9:20

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In general, there are no guarantees what happens in this region. It may read as high, it may read as low, and it may read as high one clock cycle and low the next. In some chips (especially simple 74-series logic chips), it may even cause increased supply current, though this is unlikely to be the case with FPGAs and microcontrollers.

Even if you measure the behaviour to be consistent, it's bad practice to rely on it. Since it's not specified in the datasheet, there are no guarantees that it won't silently change in a future revision of the chip.

You as the circuit designer are responsible for making sure inputs are driven to valid logic levels when you need to use them as inputs. It's not usually harmful to allow an unused GPIO to float, though.

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    \$\begingroup\$ Generally floating inputs should and are usually avoided as even if they usually are not very harmful, they can cause problems in the form of consuming more current due to inputs toggling with noise or current leaking from supply to groud if both input transistors are halfway turned on. With these FPGAs, simply turn on pull-ups or pull-downs, or the bus keeper feature for example - but it may be confusing as the input pin ia pulled to the state it was previously set to. \$\endgroup\$ Commented May 31, 2024 at 22:27

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