Different implementation between FPGA and CPLD?

Question

I have this very simple VHDL code that should implement a flip-flop with asynchronous (active low) Set and Reset. The clock (Clk) has no oscillator connected to the pin, only an input I can toggle with a switch. The code have been implemented on a real device and works as intended.

I have two questions to this:

Since no "real" clock is used would it have been better to replace the rising_edge(Clk) and simply used a elsif Clk = '1'?
If this can be considered as a pure combinatorial circuit, would it work better in a CPLD?

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Flip_Flop is port( Clk, CLR, PRE, D : in std_logic; Q, Q_not : out std_logic); end Flip_Flop; architecture Behavioral of Flip_Flop is begin process (Clk, CLR, PRE) is begin if CLR = '0' then Q <= '0'; Q_not <= '1'; elsif PRE = '0' then Q <= '1'; Q_not <= '0'; elsif rising_edge(Clk) then Q <= D; Q_not <= not D; end if; end process; end Behavioral;

If you can tell me what the difference is between a CPLD and an FPGA, then I can tell you in which one your logic works better. Deal? — Stefan Wyss
– Stefan Wyss, Commented Mar 4 at 18:50
@StefanWyss I can try. A CPLD have macrocells which are build up by pure logic gates. Whereas a FPGA also have logic gates, but also LUTs which are much more flexible. FPGAs also contains DSPs, RAM and multipliers. — Tyassin
– Tyassin, Commented Mar 4 at 20:20
"FPGAs also contains [extras]" devices may contain extras. One abstraction of early FPGAs I fondly remember: an array of GAL4V2 in a sea of configurable routing. — greybeard
– greybeard, Commented Mar 5 at 6:30

TonyM · Accepted Answer · 2025-03-04 19:56:53Z

"Since no "real" clock is used would it have been better to replace the rising_edge(Clk) and simply used a elsif Clk = '1'?"

You earlier say "I have this very simple VHDL code that should implement a flip-flop"; a positive edge-triggered D-type Flip-Flop (DFF) by the look of it. So if you're implementing a DFF with a positive-edge clock, you need to detect rising edges on the clock so ,yes, you need rising_edge(Clk) or similar.

If you detect a level elsif Clk = '1', you'll be implementing a sort-of latch. Changes on CLR or PRE while CLK is HIGH will latch any new values of D for Q and Q_not*. (Not a real latch as changes on D won't flow through to Q and Q_not.

(*Q_N is shorter and probably more commonplace, suffixing _N for active LOW).

"If this can be considered as a pure combinatorial circuit, would it work better in a CPLD?"

There's no consistent definitions of a CPLD and an FPGA but the following are good enough nearly all the time (there's exceptions to these but in the minority):

FPGA uses RAM-based configuration, CPLD uses direct non-volatile configuration
FPGA contains functions beyond programmable logic (e.g. RAM, PLL, DSP/multiplier, serdes), CPLD contains just programmable logic

Both FPGAs and CPLDs contain programmable logic, including registers that can be DFFs. And you're implementing a DFF. So both technologies can implement this just as well, there's no functional advantage of FPGA over CPLD or vice versa.

So, no, it won't functionally work better or noticeably different in a CPLD.

Just a subjective feeling, not based by market research: the time of RAM based FPGA configuration seems to be over. I used to use Xilinx XC3000 series, and loved the multiple ways to feed their configuration. At the same time I used MACH210 CPLDs, so I also have some experience here. — the busybee
– the busybee, Commented Mar 5 at 8:33
In my opinion(!) FPGA and CPLD differ mostly in the sheer number of logic cells, and then in the architecture. Therefore, these terms have a historic background. From a more abstract viewpoint, an FPGA is "just" a VCPLD, a very complex programmable logic device. :-D The fact that many (not all!) FPGA also include blocks you list is not a specific feature of FPGAs in general. -- Anyway, +1. — the busybee
– the busybee, Commented Mar 5 at 8:34
So if we take my basic design, I would suspect a CPLD to be more appropriate simply because: it is cheaper, less power hungry, no power supply sequencing and more tolerant on its IOs with regards to back-power issues? — Tyassin
– Tyassin, Commented Mar 5 at 15:32
@Tyassin Do you mean this generally, or do you have some specific FPGA and CPLD in mind? — the busybee
– the busybee, Commented Mar 5 at 16:35
@busybee I mean generally? I hope it is understood as a question. — Tyassin
– Tyassin, Commented Mar 5 at 17:11

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