Questions tagged [sequential-logic]
A digital logic circuit containing feedback, in which outputs depend not only on present values of inputs but also on past values. Sequential logic is used to implement state. Contrast with "combinatorial logic", where outputs depend only on present values of inputs, and there is no feedback.
112 questions
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Safety isolate STM32 from SRAM when power to SRAM drop?
I have an MCU connected to external SRAM (the SRAM powered from battery only and the MCU from another constant supply). The interface to SRAM is QSPI with max frequency of 104MHz. I can't guarantee ...
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1 vote
2 answers
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Clear and Preset in SR Flip Flop
I am new to learning sequential circuits and in a lecture I was taught about Preset and Clear. My doubt is that in a SR Flip Flop using NAND implementation and active low clear and Preset we should ...
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2 votes
1 answer
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How does the SN74LS107A JK flip flop avoid racing?
In the diagram below, if !CLR, Q and K are high and a clock pulse comes in. AND2 would have its output low and AND4 would be high. On the falling edge of the clock, AND2 and AND4 would both be low and ...
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1 vote
2 answers
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What is the metastable state of an SR latch?
Digital Design: Principles and Practice by John Wakerly (page 355) says that if the S and R inputs of an SR latch go from 1 to 0 simultaneously, the latch may "go into an unpredictable next state,...
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3 votes
1 answer
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Timing of a Single-Clock Sequential Logic System - Data Corruption?
I'm going through MIT's open courseware course 'Computation Structures.' The image below has caused a bit of confusion for me. I've learned how each register is made from a pair of D-latches called ...
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How to assign values to each state in a sequential circuit? [closed]
I am working on the analysis of a sequential circuit that includes D-type flip-flops, a clock signal (Clk), a reset signal, and an input ...
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5 votes
3 answers
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What is the propagation delay in flip flops?
Is this the amount of time it takes to change the output once input is placed inside? In flip flops, when we input something, the output remains constant for some time until it changes. Is this amount ...
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3 votes
4 answers
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How can flipflops sense the edges of the signals?
Latches are level triggered and flipflops are edge triggered. Latches have simple gates connected in a fashion such that they can retrieve the state and hence they are level triggered. That's fine. ...
1 vote
2 answers
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Final non-blocking assignment to a register in case of parallel if-else statement in Verilog
I have the following code: ...
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4 votes
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Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog
Please refer to the following Verilog module: ...
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0 votes
1 answer
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How are flipflops with SR, RS, S'R', Qn Qn' in both order equivalent to each other? [closed]
All images link: https://imgur.com/a/feKDXzd I want to understand the various variations of above and be able to draw any of the above circuits if I know how to draw one of them. latch (using NAND/...
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1 answer
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Trying to design a synchronous sequential counter circuit with a given sequence
I'm trying to design a counter circuit that counts 6 → 4 → 2 → 0 → 2 → 5 → 3 → 1 using T flip flops and I haven't been able to achieve it. I tried the steps below and designed the circuit below in ...
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2 votes
1 answer
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Making a 9-0 synchronous down counter using flip-flops
I've been trying to make a timer that starts from 0 then counts down at 9 to 0. I've been struggling to make it. I made state tables and diagrams and for the flipflops, but when implementing to a ...
2 votes
1 answer
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Design of non-overlapping "1010" sequence detector
Assuming that A, B, C and D are the four states. When detecting the sequence "1010", in the D state, if overlapping is not allowed, we have the following state diagram: After detecting "...
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5 votes
2 answers
878 views
Why I am getting one clock cycle delay in Verilog case statement?
I have a Verilog code here: ...
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