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I have been studying the clock muxed from this source:

https://vlsitutorials.com/glitch-free-clock-mux/

In this and many other websites, the clock mux is a flip-flop-based circuit. From what I understand, the circuit is constructed with two gated clock cells. (The gated clock cells that I mentioned are explained here)

clock mux with ff

Most of the gated clock cells I saw on the web were implemented with latches.

Why aren't latches used in the clock muxes then? Could we have used latches instead of flip-flops in the circuit?

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  • \$\begingroup\$ No it does not. I am asking whether we can use latches instead of flip flops. If you read my post in full it explains the question. It's very clear. \$\endgroup\$ Commented Aug 24 at 18:14
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    \$\begingroup\$ I am asking whether we can use latches instead of flip flops ... that is not what you asked ... Why aren't the clock muxes are also made with latches? ... please edit your post with a correction to your question \$\endgroup\$ Commented Aug 24 at 18:38
  • \$\begingroup\$ Hopefully everything is all clear now. Edited and rephrased the text. \$\endgroup\$ Commented Aug 24 at 20:28
  • \$\begingroup\$ I am really curious about this question. I would really love to hear why a latch would not work there. @Andyaka, I have rephrased my question. Could you now take another look? \$\endgroup\$ Commented Aug 24 at 21:59
  • \$\begingroup\$ Maybe you can add a logic gate version of a latch circuit. I mean it might work but, it might be more complex or, it might not lend itself so easily to the double D ff circuit shown in the link. In short, a latch can mean anything. Also, how you would implement it is of interest and, maybe you have already simulated the behaviour with a latch. If you have that would be good info to add \$\endgroup\$ Commented Aug 24 at 22:27

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A glitch-free clock mux is a specific asynchronous state machine, and there are many ways to realize it physically, including using only gates — no FFs or latches as such. But you can use either FFs or latches as long as the resulting circuit implements the abstract state machine correctly.

However, I want to point out that the circuit given by vlsitutorials.com is most definitely NOT glitch-free — in fact, it is practically guaranteed to produce glitches!

For example, suppose you have a high-to-low transition on select followed by a rising edge on clk2. This causes flop2_o to fall after its clock-to-out propagation delay. During that brief interval, both inputs to o_and2 are high, creating exactly the sort of glitch you're trying to avoid.

A correct implementation would use FFs that trigger on the falling edge of their clock.

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  • \$\begingroup\$ I see, thank you for the warning, I totally forgot the dtoq delay of the flip flop. I will try to reassess if adding a latch with its enable inverted would cause glitches in the circuit \$\endgroup\$ Commented Aug 25 at 22:07

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