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i'm beginner in verilog and digital circuits, and i have one doubt in the code below. In this code i made a state machine that saves values in a "reg" into another module in verilog. I made this code just to explain my doubt:

//STATE MACHINE module RegTest(clk,enable,reset, readData1_out); parameter State1 = 0; parameter State2 = 1; parameter State3 = 2; parameter State4 = 3; parameter State5 = 4; parameter State6 = 5; parameter State7 = 6; parameter State8 = 7; parameter State9 = 8; parameter State10 = 9; parameter Beg = 10; input clk, enable, reset; output readData1_out; wire clk,enable, reset; reg[5:0] State; reg writeEn ; reg [15:0] writeData; wire [15:0] readData1; wire writeEn_out = writeEn; RegFile registrador_component ( .dataIn(writeData), .dataOut(readData1), .clock(clk), .writeEnable(writeEn) ); defparam registrador_component.WIDTH = 16; always @(posedge clk or posedge reset) begin if (reset) begin State = Beg; end else begin case (State) Beg: begin State = State1; end State1: begin writeEn = 1 ; writeData = 10; State = State2; end State2: begin writeEn = 0 ; State = State3; end State3: begin writeEn = 1; writeData = readData1 + 10; State = State4; end State4: begin writeEn = 0 ; State = State5; end State5: begin writeEn = 1 ; writeData = readData1 + 10; State = State6; end State6: begin writeEn = 0 ; State = State7; end State7: begin writeEn = 1 ; writeData = readData1 + 10; State = State8; end State8: begin writeEn = 0 ; State = State9; end endcase end end endmodule //Example of a register file module RegFile(clock, writeEnable, dataIn, dataOut); parameter WIDTH = 16; input clock, writeEnable; input [WIDTH-1 : 0] dataIn; output [WIDTH-1 : 0] dataOut; wire [WIDTH-1 : 0] dataOut; reg [WIDTH-1 : 0] wha; assign dataOut = wha; always@( posedge clock) begin if (writeEnable) wha = dataIn; end endmodule

My doubt is, why do I need to wait 1 cycle to get the value that is stored in RegFile? Why can't I skip the State2 for example?

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You do in fact have 2 clock cycles of delay in the code you wrote above. It would help if you simulated this so you can see it for yourself, but I'll describe it.

On the first cycle, WriteEnable goes high. It takes 1 full clock cycle to be valid to other parts of the logic. So after the first clock cycle is done, WriteEnable will be available for use elsewhere.

On the second cycle, your regFile module can "see" the fact that WriteEnable went high previously. It then will put dataIn into wha signal, which gets passed to dataOut. So after the second clock cycle is done, dataOut will be available for use elsewhere. (It gets used on the third clock cycle in State 3).

This is why you need to go to state 2. State 2 allows for the 1 extra clock cycle needed for RegFile to register the output data.

Clock cycle delay is an extremely important concept to understand, so it's good that you're putting in the time when you are still new to fully grasp it.

For more information see this tutorial here, it explains registers and clock cycle delay and will be useful for you. Clock Cycle Delays and Registered Logic

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Thanks, your answer and tutorial helped me a lot to understand the functioning of this circuit. But I have two more doubts about it. I deleted the module RegFile and put the code directly in the module of the state machine. Is the same state machine, but with the code below inside: assign readData1 = wha; always@( posedge clk) begin if (writeEn) wha = writeData; end And it works without the state2 , why? Another way to skip the state2 is using "negedge" in the RegFile module, why with negedge I can skip the state2?
You should simulate this to fully understand it. Are you simulating your design? With Modelsim or any simulator you can see clearly the answers to your questions above.
Yes I'm simulating with Modelsim, I see this things in the simulator, but I can't understand perfectly wath is happening
Each time you look for the Enable signal, then do something (assign a new value) it takes 1 extra clock cycle. (Assuming you are using only the positive edge). When you start using the negative edge as well, well then the data is ready half a clock cycle sooner. That being said, you should not be using the negative edge of the clock! Use only the positive edge.

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