Programmable Logic Array

Programmable Logic Array

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  Presentation on: Programmable LogicArray (PLA) Submitted to : Faisal Bin Abdul Aziz Lecturer Dept. of CSE Comilla University Submitted by: Tipu Sultan ID: 11708003 Dept of CSE Comilla University
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  Advantages PLA architecture moreefficient than a PROM. Disadvantage PLA architecture has two sets of programmable fuses due to which PLA devices are difficult to manufacture, program and test. Programmable Logic Array (PLA): Definition: A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. The no. of programmable link sin PLA is 2n*k+ k*m+m, where as that of rom is 2n *m. BLOCK DIAGRAM OF PLA:
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  Internal construction ofas pecific PLA:
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  Implementation procedure: 1. Preparationin SOP (sum of products) form 2. Obtain the minimum SOP form to reduce the number of product terms to a minimum. 3. Decide the in put connection of the AND matrix for generating the required product term. 4. Then decide the input connections of OR matrix to generate the sum terms. 5. Decide the connections of invert matrix. 6. Program the PLA. Let’s try to implement these function f1 and f2 are given as F1=X1 X2 + X1 X’3 + X’1 X’2 X3 F2=X1 X2 + X’1 X2’X3 + X1 X’3
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  PLA Program Table: Theuse of a PLA must be consider for combinational circuits that have a large number of inputs and outputs.It is superior to a ROM for circuits that have a large number of don’t-care conditions. The example presented below demonstrates how aPLA is programmed.Bear in mind when going through the example that such a simple circuit will not require a PLA because it can be implemented more economically with SSI(Small Scale Integration ) gates.
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  Inputs x1, x2,x3 and theirrespective complemented signalsare given to programmable AND plane, there we will get AND plane outputs as P1, P2, P3called minterms. Then these signals are given to programmable OR plane to produce required output function f1 and f2 (sum of products). The below figure describes the gate level implementation of the PLA for given functionality. Related problem : Derive the PLA program table for a combinational circuit that’ squares 3-bit number. Solution: PLA program table: