This question is about how multiple DDR5 DIMMs in the same memory channel are wired to the processor. This is mostly an electrical engineering question, and the goal to answer this question:
Will re-seating a processor increase the likelihood that the second DIMM per channel will function, specifically in the case when both memory channels are known to function populated with only one DIMM each (ie, both memory channels are functional)? All memory modules are known good.
I looked around at DDR5 documentation and there is quite a bit related to performance and ranks, but none that I could find about how they are physically wired to their memory bus in the layout.
My thinking is this: if the channels are each independent, and a series of memory modules on the same channel is wired as a parallel bus (with some kind of chip- or address-selector), then reseating the processor is unlikely to solve the problem when both channels are known to function. Is this true?
I have an AM5 system that sees the memory in one DIMM slot of each memory channel for the processor, but when 2x DIMMs per channel are installed, the system will not POST.
I could just reseat the processor and find out, but I would like to understand the technical details at the implementation level (at least a little better) before just tearing things apart and crossing my fingers.
